4.2.1.2 Configuration Cycles
Devices on the PCI bus must comply with PCI protocol that allows configuration of that device by
software. In this system, configuration mechanism #1 (as described in the PCI Local Bus
specification Rev. 2.1) is employed. This method uses two 32-bit registers for initiating a
configuration cycle for accessing the configuration space of a PCI device. The configuration
address register (CONFIG_ADDRESS) at 0CF8h holds a value that specifies the PCI bus, PCI
device, and specific register to be accessed. The configuration data register (CONFIG_DATA) at
0CFCh contains the configuration data.
PCI Configuration Address Register PCI Configuration Data Register
I/O Port 0CF8h, R/W, (32-bit access only) I/O Port 0CFCh, R/W, (8-, 16-, 32-bit access)
Bit Function Bit Function
31 Configuration Enable 31..0 Configuration Data.
0 = Disabled
1 = Enable
30..24 Reserved - read/write 0s
23..16 Bus Number. Selects PCI bus
15..11 PCI Device Number. Selects PCI
device for access
10..8 Function Number. Selects function of
selected PCI device.
7..2 Register Index. Specifies config. reg.
1,0 Configuration Cycle Type ID.
00 = Type 0
01 = Type 1
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Two types of configuration cycles are used. A Type 0 (zero) cycle is targeted to a device on the
PCI bus on which the cycle is running. A Type 1 cycle is targeted to a device on a downstream PCI
bus as identified by bus number bits <23..16>. A PCI bridge may convert a Type 1 to a Type 0 if
it's destined for a device being serviced by that bridge or it may forward the Type 1 cycle
unmodified if it is destined for a device being serviced by a downstream bridge. Figure 4-2 shows
the configuration cycle format and how the loading of 0CF8h results in a Type 0 configuration
cycle on the PCI bus. The Device Number (bits <15..11> determines which one of the AD31..11
lines is to be asserted high for the IDSEL signal, which acts as a "chip select" function for the PCI
device to be configured. The function number (CF8h, bits <10..8>) is used to select a particular
function within a PCI component.
87 2 1 0 [1]
31 24 23 16 15 11 10
Bus Device Function Register
Reserved
Register 0CF8h Number Number Number Index
Results in:
AD31..0 Function Register
IDSEL (only one signal line asserted)
(w/Type 0 Number Index
Config. Cycle)
NOTES:
[1] Bits <1,0> : 00 = Type 0 Cycle, 01 = Type 1 cycle
Type 1 cycle only. Reserved on Type 0 cycle.
Figure 4-2. Configuration Cycle
Table 4-1 shows the standard configuration access data for components and slots residing on a PCI
bus.
Table 4-1. PCI Device Configuration Access Data
Table 4-1.
PCI Component Configuration Access Data (iPAQ 1.x / iPAQ 2.0 [1])
PCI IDSEL
PCI Component Device ID Bus # Device # Function # Wired to:
82810E / 82815 GMCH: --
Memory Controller 2500h / 1130h 0 0 (00h) 0
PCI/PCI (AGP) Bridge 2501h / 1131h 0 1 (01h) 0
Graphics Controller 2502h / 1132h 0 2 (02h) 0
82801AA ICH / 82801BA ICH2: --
PCI/PCI Bridge 2418h / 244Eh 0 30 (1Eh) 0
LPC Bridge 2410h / 2440h 0 31 (1Fh) 0
EIDE Controller 2411h / 244Bh 0 31 (1Fh) 1
USB I/F #1 2412h / 2442h 0 31 (1Fh) 2
SMBus Controller 2413h / 2443h 0 31 (1Fh) 3
Reserved / USB I/F #2 na / 2444h na / 0 na / 31 (1Fh) na / 4
AC97 Audio Controller 2415h / 2445h 0 31 (1Fh) 5
AC97 Modem Controller na na na na
Na / NIC Function na / 2449h na / 2 na / 8 (08h) na / 0
82559 Network I/F Controller [2] 1229h 2 31 (1Fh) 0 AD22
NOTES:
Vender ID = 8086 for all components.
82810e and 82801AA used in iPAQ 1.0 and 1.2 systems.
82815 and 82801BA used fin iPAQ 2.0 systems
na = Not applicable or implemented on these systems.
[1] Entries and values apply to both system types unless divided by forward slash.
[2] iPAQ 1.0 and 1.2 systems only.
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The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space
of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration data
(Figure 4-3), of which the first 64 bytes comprise the configuration space header.
Register
Register
Index
Index
31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0
FCh
FCh
Device-Specific Area Device-Specific Area
40h
40h
3Ch
Min. Lat. Min. GNT Int. Pin Int. Line Bridge Control Int. Pin Int. Line
3Ch
38h
Reserved Expansion ROM Base Address
38h
34h
Reserved Reserved
34h
30h
Expansion ROM Base Address I/O Limit Upper 16 Bits I/O Base Upper 16 Bits
30h
2Ch
Subsystem ID Subsystem Vendor ID Prefetchable Limit Upper 32 Bits
2Ch
28h
28h
Card Bus CIS Pointer Prefetchable Base Upper 32 Bits
24h
Prefetch. Mem. Limit Prefetch. Mem. Base
Configuration
20h
Memory Limit Memory Base
Space
1Ch
Secondary Status I/O Limit I/O Base
Header Base Address Registers
18h
2nd Sub. Bus # Sec. Bus # Pri. Bus #
Base Address Registers
10h
10h
0Ch
BIST Hdr. Type Lat. Timer Line Size BIST Hdr. Type Lat. Timer Line Size
0Ch
08h
08h
Class Code Revision ID Class Code Revision ID
04h 04h
Status Command Status Command
00h
00h
Device ID Vendor ID Device ID Vendor ID
PCI Configuration Space Type 1
PCI Configuration Space Type 0
Data required by PCI protocol
Not required
Figure 4-3. PCI Configuration Space Mapping
Each PCI device is identified with a vendor ID (assigned to the vendor by the PCI Special Interest
Group) and a device ID (assigned by the vendor). The device and vendor IDs for the devices on
the system board are listed (previously) in Table 4-1.
4.2.2 PCI SUB-BUSSES
The chipset implements two data busses that are supplementary in operation to the PCI bus:
The chipset implements a Hub Link bus between the GMCH and the ICH. This bus is transparent
to software and not accessible for expansion purposes.
The 82801 ICH implements a Low Pin Count (LPC) bus for handling transactions to and from the
47B357 Super I/O Controller as well as the 82802 FWH. The LPC bus transfers data a nibble (4
bits) at a time at a 33-MHz rate. Generally transparent in operation, the LPC bus becomes a factor
primarily during the configuration of DMA channel modes (see section 4.4.3 "DMA").
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4.2.3 PCI CONFIGURATION
PCI bus operations require the configuration of certain parameters such as PCI IRQ routing, DMA
channel configuration, RTC control, port decode ranges, and power management options. These
parameters are handled by the LPC I/F bridge function (PCI function #0, device 31) of the ICH
component and configured through the PCI configuration space registers listed in Table 4-2.
Configuration is provided by BIOS at power-up but re-configurable by software.
Table 4-2. LPC Bridge Configuration Registers (ICH, Function 0)
Table 4-2.
LPC Bridge Configuration Registers
(ICH/ICH2, Function 0, Device 31)
PCI
PCI
Config. Reset
Config. Reset
Addr. Register Value
Addr. Register Value
00, 01h Vendor ID 8086h 8Ah Device 31 Error Status 00h
02, 03h Device ID [2] 90, 91h PCI DMA Configuration 0000h
04, 05h Command 000Fh A0-CFh Power Management
06, 07h Status 0280h D0-D3h General Control 0's
08h Revision ID 00h D4-D7h General Status F00h
0A-0Bh Class Code 0106h D8h RTC Configuration 00h
0Eh Header Type 80h E0h LPC COM Port Dec. Range 00h
40-43h ACPI Base Address 1 E1h LPC FDD & LPT Dec. Rge 00h
44h ACPI Control 00h E2h LPC Audio Dec. Range 80h
4E, 4Fh BIOS Control 0000h E3h FW H Decode Enable FFh
54h TCO Control 00h E4, E5h LPC I/F Decode Range 1 0000h
58-5Bh GPIO Base Address 1 E6, E7h LPC I/F Enables 0000h
5Ch GPIO Control 00h E8h FW H Select 00
60-63h INTA-D Routing Cntrl. 80h [1] EC, EDh LPC I/F Decode Range 2 0000h
64h Serial IRQ Control 10h EE, EFh Reserved --
65-87h Reserved -- F0h Reserved --
88h Dev. 31 Error Config. 00h F2h Function Disable Register 00h
NOTE:
[1] Value for each byte.
[2] ICH = 2410h, ICH2 = 2440h
Assume unmarked locations/gaps as reserved.
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4 .3 SYSTEM RESOURCES
This section describes the availability and basic control of major subsystems, otherwise known as
resource allocation or simply "system resources." System resources are provided on a priority
basis through hardware interrupts and DMA requests and grants.
4.3.1 INTERRUPTS
The microprocessor uses two types of hardware interrupts; maskable and nonmaskable. A
maskable interrupt can be enabled or disabled within the microprocessor by the use of the STI and
CLI instructions. A nonmaskable interrupt cannot be masked off within the microprocessor,
although it may be inhibited by hardware or software means external to the microprocessor.
4.3.1.1 Maskable Interrupts
The maskable interrupt is a hardware-generated signal used by peripheral functions within the
system to get the attention of the microprocessor. Peripheral functions produce a unique INTA-H
(PCI) or IRQ0-15 (ISA) signal that is routed to interrupt processing logic that asserts the interrupt
(INTR-) input to the microprocessor. The microprocessor halts execution to determine the source
of the interrupt and then services the peripheral as appropriate. Figure 4-4 shows the routing of
PCI and ISA interrupts. Most IRQs are routed through the I/O controller, which contains a
serializing function. A serialized interrupt stream is applied to the 82801 ICH.
I/O Controller
IRQ3..7,
9..12,
14,15 Interrupt Serial IRQ
I/O &
Serializer
SM Functions 82801
ICH
IDE INTR-
IRQ14,15
Hard Drives Interrupt
Microprocessor
APIC Bus
Processing
INTA-..H-
PCI Peripherals
Figure 4-4. Maskable Interrupt Processing, Block Diagram
The 82801 ICH2 component can be configured (through the Setup utility) to handle interrupts in
one of two modes of operation:
8259 mode
APIC mode
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8259 Mode
In 8259-Mode, interrupts IRQ0-IRQ15 are handled in the conventional (AT-system) method using
logic that is the equivalent of two 8259 interrupt controllers. Table 4-3 lists the standard source
configuration for maskable interrupts and their priorities in 8259 mode. If more than one interrupt
is pending, the highest priority (lowest number) is processed first.
Table 4-3. Maskable Interrupt Priorities and Assignments
Table 4-3.
Maskable Interrupt Priorities and Assignments
Priority Signal Label Source (Typical)
1 IRQ0 Interval timer 1, counter 0
2 IRQ1 Keyboard
3 IRQ8- Real-time clock
4 IRQ9 Unused
5 IRQ10 Unused
6 IRQ11 Unused
7 IRQ12 Mouse
8 IRQ13 Coprocessor (math)
9 IRQ14 IDE primary I/F
10 IRQ15 IDE secondary I/F
11 IRQ3 Serial port (COM2)
12 IRQ4 Serial port (COM1)
13 IRQ5 Unused
14 IRQ6 Diskette drive controller
15 IRQ7 Parallel port (LPT1)
-- IRQ2 NOT AVAILABLE (Cascade from interrupt controller 2)
APIC Mode
The Advanced Programmable Interrupt Controller (APIC) mode enhances interrupt-processing
performance with the following advantages:
Eliminating the processor's interrupt acknowledge cycle by using a separate APIC bus.
Programmable interrupt priority.
Additional interrupts (total of 24).
NOTE: The APIC mode is supported by Windows NT/2000 operating systems. Systems
using the Windows 95 or 98 operating system will need to run in 8259 mode. The mode is
selectable through the Setup utility (access with F10 key during boot sequence).
Maskable Interrupt processing is controlled and monitored through standard AT-type I/O-mapped
registers. These registers are listed in Table 4-4.
Table 4-4. Maskable Interrupt Control Registers
Table 4-4.
Maskable Interrupt Control Registers
I/O Port Register
020h Base Address, Int. Cntlr. 1
021h Initialization Command Word 2-4, Int. Cntlr. 1
0A0h Base Address, Int. Cntlr. 2
0A1h Initialization Command Word 2-4, Int. Cntlr. 2
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4.3.1.2 Non-Maskable Interrupts
Non-maskable interrupts cannot be masked (inhibited) within the microprocessor itself but may be
maskable by software using logic external to the microprocessor. There are two non-maskable
interrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable
interrupts, with the SMI- having top priority over all interrupts including the NMI-.
NMI- Generation
The Non-Maskable Interrupt (NMI-) signal can be generated by either a parity error detected on a
PCI bus (activating SERR- or PERR-) or by an internal processor error (activating IERRA or
IERRB).
The SERR- and PERR- signals are routed through the ICH component, which in turn activates the
NMI to the microprocessor. The NMI Status Register at I/O port 061h contains NMI source and
status data as follows:
NMI Status Register 61h
Bit Function
7 NMI Status:
0 = No NMI from system board parity error.
1 = NMI requested, read only
6 IOCHK- NMI:
0 = No NMI from IOCHK-
1 = IOCHK- is active (low), NMI requested, read only
5 Interval Timer 1, Counter 2 (Speaker) Status
4 Refresh Indicator (toggles with every refresh)
3 IOCHK- NMI Enable/Disable:
0 = NMI from IOCHK- enabled
1 = NMI from IOCHK- disabled and cleared (R/W)
2 System Board Parity Error (PERR/SERR) NMI Enable:
0 = Parity error NMI enabled
1 = Parity error NMI disabled and cleared (R/W)
1 Speaker Data (R/W)
0 Inteval Timer 1, Counter 2 Gate Signal (R/W)
0 = Counter 2 disabled
1 = Counter 2 enabled
Functions not related to NMI activity.
After the active NMI has been processed, status bits <7> or <6> are cleared by pulsing bits <2> or
<3> respectively. The NMI Enable Register (070h, <7>) is used to enable/disable the NMI signal.
Writing 80h to this register masks generation of the NMI-. Note that the lower six bits of register at
I/O port 70h affect RTC operation and should be considered when changing NMI- generation
status.
SMI- Generation
The SMI- (System Management Interrupt) is typically used for power management functions.
When power management is enabled, inactivity timers are monitored. When a timer times out,
SMI- is asserted and invokes the microprocessor's SMI handler. The SMI- handler works with the
APM BIOS to service the SMI- according to the cause of the timeout. Although the SMI- is
primarily used for power managment the interrupt is also employed for the QuickLock/QuickBlank
functions as well.
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4.3.2 DIRECT MEMORY ACCESS
Direct Memory Access (DMA) is a method by which a device accesses system memory without
involving the microprocessor. Although the DMA method has been traditionally used to transfer
blocks of data to or from an ISA I/O device, PCI devices may also use DMA operation as well.
The DMA method reduces the amount of CPU interactions with memory, freeing the CPU for
other processing tasks.
NOTE: This section describes DMA in general. For detailed information regarding
DMA operation, refer to the data manual for the Intel 82801 I/O Controller Hub.
The 82801 component includes the equivalent of two 8237 DMA controllers cascaded together to
provide eight DMA channels, each (excepting channel 4) configurable to a specific device. Table
4-5 lists the default configuration of the DMA channels.
Table 4-5. Default DMA Channel Assignments And Register I/O Ports
Table 4-5
DMA Channel Assignments And Register Ports
DMA Channel Function I/O Port
Controller 1 (byte transfers) Control registers 000h-00Eh
0 Unused Page register 087h
1 Audio subsystem Page register 083h
2 Diskette drive Page register 081h
3 Parallel port (ECP or EPP mode) Page register 082h
Controller 2 (word transfers) Control registers 0C0h-0DEh
4 Cascade for controller 1 n/a
5 Unused Page register 08Bh
6 Unused Page register 089h
7 Unused Page register 08Ah
Refresh 08Fh [see note]
NOTE:
The DMA memory page register for the refresh channel must be
programmed with 00h for proper operation.
All channels in DMA controller 1 operate at a higher priority than those in controller 2. Note that
channel 4 is not available for use other than its cascading function for controller 1. The DMA
controller 2 can transfer words only on an even address boundary. The DMA controller and page
register define a 24-bit address that allows data transfers within the address space of the CPU.
In addition to device configuration, each channel can be configured (through PCI Configuration
Registers) for one of two modes of operation:
LPC DMA Mode - Uses the LPC bus to communicate DMA channel control and is
implemented for devices using DMA through the I/O controller such as the diskette drive
controller.
PC/PCI DMA Mode - Uses the REQ#/GNT# signals to communicate DMA channel control
and is used by PCI expansion devices.
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4 .4 SYSTEM CLOCK DISTRIBUTION
These systems use an Intel CK-type clock generator and crystal for generating the clock signals
required by the system board components. Table 4-6 lists the system board clock signals and how
they are distributed.
Table 4-6. Clock Generation and Distribution
Table 4-6
Clock Generation and Distribution
Frequncy Source Destination
100 or 133 MHz CK Processor, GMCH, DIMM sockets
66 MHz CK GMCH, ICH2, AGP slot
48 MHz CK GMCH, ICH/ICH2, I/O Cntlr.
33 MHz CK Processor, ICH/ICH2, PCI Slots
14.31818 MHz Crystal CK
14.31818 MHz CK ICH/ICH2, I/O Cntlr., and (on iPAQ 2.0) audio codec
Certain clock outputs are turned off during reduced power modes to conserve energy. Clock output
control is handled through the SMBus interface by BIOS.
4 .5 REAL-TIME CLOCK AND CONFIGURATION MEMORY
The Real-time clock (RTC) and configuration memory (also referred to as "CMOS") functions are
provided by the ICH component and is MC146818-compatible. As shown in the following figure,
the ICH component provides 256 bytes of battery-backed RAM divided into two 128-byte
configuration memory areas. The RTC uses the first 14 bytes (00-0Dh) of the standard memory
area. All locations of the standard memory area (00-7Fh) can be directly accessed using
conventional OUT and IN assembly language instructions through I/O ports 70h/71h, although the
suggested method is to use the INT15 AX=E823h BIOS call.
82801
Register D
0Dh
FFh
Register C
0Ch
Register B
0Bh Extended Config.
Register A
0Ah Memory Area
Year
09h (128 bytes)
Month
08h
80h
Date of Month
07h
7Fh
Day of Week
06h
Hours (Alarm) Standard Config.
05h
Memory Area
Hours (Timer)
04h
(114 bytes)
Minutes (Alarm)
03h
0Eh
Minutes (Timer)
02h
0Dh
RTC Area
Seconds (Alarm)
01h
(14 bytes)
Seconds (Timer) 00h
00h
CMOS
Figure 4-5. Configuration Memory Map
A lithium 3-VDC battery is used for maintaining the RTC and configuration memory while the
system is powered down. The battery is located in a battery holder on the system board is replaced
with a Renata CR2032 or equivalent 3-VDC lithium battery.
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Chapter 4 System Support
4.5.1 CLEARING CMOS
NOTE: There is no provision for clearing the contents of CMOS in iPAQ 1.0/1.2
systems. Recovery from a suspected corrupted CMOS is by using the Power Button
Override function as described in section 4.5.2.
The contents of configuration memory (including the Power-On Password) can be cleared on
iPAQ 2.0 systems using the following procedure:
1. Turn off the unit.
2. Disconnect the AC power cord from the outlet and/or system unit.
3. Remove the chassis hood (cover).
4. Insert a non-metallic object (such as a pencil eraser) through the CMOS clear button access
hole and press and release the CMOS clear button.
5. Replace the chassis hood (cover).
6. Reconnect the AC power cord to the outlet and/or system unit.
7. Turn the unit on.
To clear only the Power-On Password refer to section 4.6.1.1.
4.5.2 CMOS ARCHIVE AND RESTORE
On iPAQ 1.0/1.2 systems, the BIOS saves a copy of NVRAM (CMOS contents, password(s) and
other system variables) in a portion of the flash ROM during the boot sequence. Should the system
become un-usable, the last good copy of NVRAM data can be restored with the Power Button
Override function. This function is invoked with the following procedure:
1. With the unit powered down, press and release the power button.
2. Immediately after releasing the power button in step 1, press and hold the power button until
the unit powers down. This action will be recorded as a Power Button Override event.
With the next startup sequence the BIOS will detect the occurrence of the Power Button Override
event and will load the backup copy of NVRAM from the ROM to the CMOS.
NOTE: The Power Button Override feature does not allow quick cycling of the system
(turning on then off). If the power cord is disconnected during the POST routine, the
splash screen image may become corrupted, requiring a re-flashing of the ROM (refer to
chapter 8, BIOS ROM).
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4.5.3 STANDARD CMOS LOCATIONS
Table 4-7 and the following paragraphs describe standard configuration memory locations 0Ah-
3Fh. These locations are accessible using OUT/IN assembly language instructions using port
70/71h or BIOS function INT15, AX=E823h.
Table 4-7. Configuration Memory (CMOS) Map
Table 4-7.
Configuration Memory (CMOS) Map
Location Function Location Function
00-0Dh Real-time clock 24h System board ID
0Eh Diagnostic status 25h System architecture data
0Fh System reset code 26h Auxiliary peripheral configuration
10h Diskette drive type 27h Speed control external drive
11h Reserved 28h Expanded/base mem. size, IRQ12
12h Hard drive type 29h Miscellaneous configuration
13h Security functions 2Ah Hard drive timeout
14h Equipment installed 2Bh System inactivity timeout
15h Base memory size, low byte/KB 2Ch Monitor timeout, Num Lock Cntrl
16h Base memory size, high byte/KB 2Dh Additional flags
17h Extended memory, low byte/KB 2Eh-2Fh Checksum of locations 10h-2Dh
18h Extended memory, high byte/KB 30h-31h Total extended memory tested
19h Hard drive 1, primary controller 32h Century
1Ah Hard drive 2, primary controller 33h Miscellaneous flags set by BIOS
1Bh Hard drive 1, secondary controller 34h International language
1Ch Hard drive 2, secondary controller 35h APM status flags
1Dh Enhanced hard drive support 36h ECC POST test single bit
1Eh Reserved 37h-3Fh Power-on password
1Fh Power management functions 40-FFh Feature Control/Status
NOTES:
Assume unmarked gaps are reserved.
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Chapter 4 System Support
RTC Control Register A, Byte 0Ah
Bit Function
7 Update in Progress. Read only.
0 = Time update will not occur before 2444 us
1 = Time update will occur within 2444 us
6..4 Divider Chain Control. R/W.
00x = Oscillator disabled.
010 = Normal operation (time base frequency = 32.768 KHz).
11x = Divider chain reset.
3..0 Periodic Interrupt Control. R/W. Specifies the periodic interrupt interval.
0000 = none 1000 = 3.90625 ms
0001 = 3.90625 ms 1001 = 7.8125 ms
0010 = 7.8125 ms 1010 = 15. 625 ms
0011 = 122.070 us 1011 = 31.25 ms
0100 = 244.141 us 1100 = 62.50 ms
0101 = 488.281 us 1101 = 125 ms
0110 = 976.562 us 1110 = 250 ms
0111 = 1.953125 ms 1111 = 500 ms
RTC Control Register B, Byte 0Bh
Bit Function
7 Time Update Enable/disable
0 = Normal operation, 1 = Disable time updating for time set
6 Periodic Interrupt Enable/Disable.
0 = Disable, 1 = Enable interval specified by Register A
5 Alarm Interrupt Enable/disable
0 = Disabled, 1 = Enabled
4 End-of-Update Interrupt Enable/Disable
0 = Disabled, 1 = Enabled
3 Reserved (read 0)
2 Time/Date Format Select
0 = BCD format, 1 = Binary format
1 Time Mode
0 = 12-hour mode, 1 = 24-hour mode
0 Automatic Daylight Savings Time Enable/Disable
0 = Disable
1 = Enable (Advance 1 hour on 1st Sunday in April, retreat 1 hour on last Sunday in
October).
RTC Status Register C, Byte 0Ch
Bit Function
7 If set, interrupt output signal active (read only)
6 If set, indicates periodic interrupt flag
5 If set, indicates alarm interrupt
4 If set, indicates end-of-update interrupt
3..0 Reserved
RTC Status Register D, Byte 0Dh
Bit Function
7 RTC Power Status
0 = RTC has lost power
1 = RTC has not lost power
6..0 Reserved
Configuration Byte 0Eh, Diagnostic Status
Default Value = 00h
This byte contains diagnostic status data.
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Configuration Byte 0Fh, System Reset Code
Default Value = 00h
This byte contains the system reset code.
Configuration Byte 10h, Diskette Drive Type
Bit Function
7..4 Primary (Drive A) Diskette Drive Type
3..0 Secondary (Drive B) Diskette Drive Type
Valid values for bits <7..4> and bits <3..0>:
0000 = Not installed
0001 = 360-KB drive
0010 = 1.2-MB drive
0011 = 720-KB drive
0100 = 1.44-MB/1.25-MB drive
0110 = 2.88-MB drive
(all other values reserved)
Configuration Byte 12h, Hard Drive Type
Bit Function
7..4 Primary Controller 1, Hard Drive 1 Type:
0000 = none 1000 = Type 8
0001 = Type 1 1001 = Type 9
0010 = Type 2 1010 = Type 10
0011 = Type 3 1011 = Type 11
0100 = Type 4 1100 = Type 12
0101 = Type 5 1101 = Type 13
0110 = Type 6 1110 = Type 14
0111 = Type 7 1111 = other (use bytes 19h)
3..0 Primary Controller 1, Hard Drive 2 Type:
0000 = none 1000 = Type 8
0001 = Type 1 1001 = Type 9
0010 = Type 2 1010 = Type 10
0011 = Type 3 1011 = Type 11
0100 = Type 4 1100 = Type 12
0101 = Type 5 1101 = Type 13
0110 = Type 6 1110 = Type 14
0111 = Type 7 1111 = other (use bytes 1Ah)
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Chapter 4 System Support
Configuration Byte 13h, Security Functions
Default Value = 00h
Bit Function
7 Reserved
6 QuickBlank Enable After Standby:
0 = Disable
1 = Enable
5 Administrator Password:
0 = Not present
1 = Present
4 Reserved
3 Diskette Boot Enable:
0 = Enable
1 = Disable
2 QuickLock Enable:
0 = Disable
1 = Enable
1 Network Server Mode/Security Lock Override:
0 = Disable
1 = Enable
0 Password State (Set by BIOS at Power-up)
0 = Not set
1 = Set
Configuration Byte 14h, Equipment Installed
Default Value (standard configuration) = 03h
Bit Function
7,6 No. of Diskette Drives Installed:
00 = 1 drive 10 = 3 drives
01 = 2 drives 11 = 4 drives
5..2 Reserved
1 Coprocessor Present
0 = Coprocessor not installed
1 = Coprocessor installed
0 Diskette Drives Present
0 = No diskette drives installed
1 = Diskette drive(s) installed
Configuration Bytes 15h and 16h, Base Memory Size
Default Value = 280h
Bytes 15h and 16h hold a 16-bit value that specifies the base memory size in 1-KB (1024)
increments. Valid base memory sizes are 512 and 640 kilobytes .
Configuration Bytes 17h and 18h, Extended Memory Size
Bytes 17h and 18h hold a 16-bit value that specifies the extended memory size in 1-KB
increments.
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Technical Reference Guide
Configuration Bytes 19h-1Ch, Hard Drive Types
Byte 19h contains the hard drive type for drive 1 of the primary controller if byte 12h bits <7..4>
hold 1111b. Byte 1Ah contains the hard drive type for drive 2 of the primary controller if byte 12h
bits <3..0> hold 1111b. Bytes1Bh and 1Ch contain the hard drive types for hard drives 1 and 2 of
the secondary controller.
Configuration Byte 1Dh, Enhanced IDE Hard Drive Support
Default Value = F0h
Bit Function
7 EIDE - Drive C (83h)
6 EIDE - Drive D (82h)
5 EIDE - Drive E (81h)
4 EIDE - Drive F (80h)
3..0 Reserved
Values for bits <7..4> :
0 = Disable
1 = Enable for auto-configure
Configuration Byte 1Fh, Power Management Functions
Default Value = 00h
Bit Function
7..4 Reserved
3 Slow Processor Clock for Low Power Mode
0 = Processor runs at full speed
1 = Processor runs at slow speed
2 Reserved
1 Monitor Off Mode
0 = Turn monitor power off after 45 minutes in
standby
1 = Leave monitor power on
0 Energy Saver Mode Indicator (Blinking LED)
0 = Disable
1 = Enable
Configuration Byte 24h, System Board Identification
Default Value = 7Eh
Configuration memory location 24h holds the system board ID.
Configuration Byte 25h, System Architecture Data
Default Value = 0Bh
Bit Function
7..4 Reserved
3 Unmapping of ROM:
0 = Allowed
1 = Not allowed
2 Reserved
1,0 Diagnostic Status Byte Address
00 = Memory locations 80C00000h-80C00004h
01 = I/O ports 878h-87Ch
11 = neither place
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Chapter 4 System Support
Configuration Byte 26h, Auxiliary Peripheral Configuration
Default Value = 00h
Bit Function
7,6 I/O Delay Select
00 = 420 ns (default)
01 = 300 ns
10 = 2600 ns
11 = 540 ns
5 Alternative A20 Switching
0 = Disable port 92 mode
1 = Enable port 92 mode
4 Bi-directional Print Port Mode
0 = Disabled
1 = Enabled
3 Graphics Type
0 = Color
1 = Monochrome
2 Hard Drive Primary/Secondary Address Select:
0 = Primary
1 = Secondary
1 Diskette I/O Port
0 = Primary
1 = Secondary
0 Diskette I/O Port Enable
0 = Primary
1 = Secondary
Configuration Byte 27h, Speed Control/External Drive
Default Value = 00h
Bit Function
7 Boot Speed
0 = Max MHz
1 = Fast speed
6..0 Reserved
Configuration Byte 28h, Expanded and Base Memory, IRQ12 Select
Default Value = 00h
Bit Function
7 IRQ12 Select
0 = Mouse
1 = Expansion bus
6,5 Base Memory Size:
00 = 640 KB
01 = 512 KB
10 = 256 KB
11 = Invalid
4..0 Internal Compaq Memory:
00000 = None
00001 = 512 KB
00010 = 1 MB
00011 = 1.5 MB
11111 = 15.5 MB
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Technical Reference Guide
Configuration Byte 29h, Miscellaneous Configuration Data
Default Value = 00h
Bit Function
7..5 Reserved
4 Primary Hard Drive Enable (Non-PCI IDE Controllers)
0 = Disable
1 = Enable
3..0 Reserved
Configuration Byte 2Ah, Hard Drive Timeout
Default Value = 02h
Bit Function
7..5 Reserved
4..0 Hard Drive Timeout (index to SIT timeout record)
Configuration Byte 2Bh, System Inactivity Timeout
Default Value = 23h
Bit Function
7 Reserved
6,5 Power Conservation Boot
00 = Reserved
01 = PC on
10 = PC off
11 = Reserved
4..0 System Inactive Timeout. (Index to SIT system timeout
record)
00000 = Disabled
Configuration Byte 2Ch, ScreenSave and NUMLOCK Control
Default Value = 00h
Bit Function
7 Reserved
6 Numlock Control
0 = Numlock off at power on
1 = Numlock on at power on
5 Screen Blank Control:
0 = No screen blank
1 = Screen blank w/QuickLock
4..0 ScreenSave Timeout. (Index to SIT monitor timeout record)
000000 = Disabled
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Chapter 4 System Support
Configuration Byte 2Dh, Additional Flags
Default Value = 00h
Bit Function
7..5 Reserved
4 Memory Test
0 = Test memory on power up only
1 = Test memory on warm boot
3 POST Error Handling (BIOS Defined)
0 = Display "Press F1 to Continue" on error
1 = Skip F1 message
2..0 Reserved
Configuration Byte 2Eh, 2Fh, Checksum
These bytes hold the checksum of bytes 10h to 2Dh.
Configuration Byte 30h, 31h, Total Extended Memory Tested
This location holds the amount of system memory that checked good during the POST.
Configuration Byte 32h, Century
This location holds the Century value in a binary coded decimal (BCD) format.
Configuration Byte 33h, Miscellaneous Flags
Default Value = 80h
Bit Function
7 Memory Above 640 KB
0 = No, 1 = Yes
6 Reserved
5 W eitek Numeric Coprocessor Present:
0 = Not installed, 1 = Installed
4 Standard Numeric Coprocessor Present:
0 = Not installed, 1 = Installed
3..0 Reserved
Configuration Byte 34h, International Language Support
Default Value = 00h
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Technical Reference Guide
Configuration Byte 35h, APM Status Flags
Default Value = 11h
Bit Function
7..6 Power Conservation State:
00 = Ready
01 = Standby
10 = Suspend
11 = Off
5,4 Reserved
3 32-bit Connection:
0 = Disconnected, 1 = Connected
2 16-bit Connection
0 = Disconnected, 1 = Connected
1 Real Mode Connection
0 = Disconnected, 1 = Connected
0 Power Management Enable:
0 = Disabled
1 = Enabled
Configuration Byte 36h, ECC POST Test Single Bit Errors
Default Value = 01h
Bit Function
7 Row 7 Error Detect
6 Row 6 Error Detect
5 Row 5 Error Detect
4 Row 4 Error Detect
3 Row 3 Error Detect
2 Row 2 Error Detect
1 Row 1 Error Detect
0 Row 0 Error Detect
0 = No single bit error detected.
1 = Single bit error detected.
Configuration Byte 37h-3Fh, Power-On Password
These eight locations hold the power-on password.
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Chapter 4 System Support
4.6 SYSTEM MANAGEMENT
This section describes functions having to do with security, power management, temperature, and
overall status. These functions are handled by hardware and firmware (BIOS) and generally
configured through the Setup utility.
4.6.1 SECURITY FUNCTIONS
These systems include various features that provide different levels of security. Note that this
subsection describes only the hardware functionality (including that supported by Setup) and
does not describe security features that may be provided by the operating system and application
software.
4.6.1.1 Passwords
CAUTION: Both iPAQ 1.x and 2.0 systems support the use of Setup and Power-On
! passwords and implement them in the same way. An iPAQ 2.0 system with enabled but
forgotten passwords may be restarted after clearing CMOS with the CMOS clear button
(section 4.5.1). However, the iPAQ 1.0/1.2 does not include a CMOS clear button and
enabling and then forgetting both the Setup and Power-On passwords on an iPAQ 1.0/1.2
system will require invoking a special utility with a service password based on the unit
serial number and date. The utility can be invoked only as a network application
through Compaq Customer Support.
Setup Password
The Setup utility may be configured to be always changeable or changeable only by entering a
password. The password is held on CMOS and if enabled and forgotten, will inhibit any changes
offered by the Setup utility. Refer to the previous Caution for dealing with forgotten passwords.
Power-On Password
These systems support the use of a power-on password, which may be enabled or disabled through
the Setup utility. The password is stored in configuration memory (CMOS). If enabled and then
forgotten on iPAQ 1.0/1.2 systems refer to the previous Caution statement. Forgotten Power-On
passwords for iPAQ 2.0 systems can be cleared using the procedure described below or the entire
CMOS be cleared (refer to section 4.5.1).
To clear only the Power-On password, use the following procedure:
1. Turn off the system and disconnect the AC power cord from the outlet and/or system unit.
2. Remove the cover (hood). Insure that all system board LEDs are off (not illuminated).
3. Locate the password header/jumper (labeled E49 on these systems) and remove the jumper
from pins 1 and 2 and place on (just) pin 2 (for safekeeping).
4. Replace the cover.
5. Re-connect the AC power cord to the AC outlet and/or system unit.
6. Turn on the system. The POST routine will clear and disable the password.
7. To re-enable the password feature, repeat steps 1-6, replacing the jumper on pins 1 and 2 of
header E49.
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Technical Reference Guide
DriveLock Password
These systems support the DriveLock security feature for a compatible hard drive installed in the
Multibay. When enabled, DriveLock prevents unauthorized access to hard drive data by requiring
either a master DriveLock or a user DriveLock password to be entered. Although this function is
controlled through the Setup utility, the password information is stored in a reserved area on the
hard drive so that the password(s) will stay or move with the drive.
CAUTION: The DriveLock feature is designed primarily for business environments
! where removable hard drives may be moved from system to system. Since forgetting both
DriveLock passwords for a particular drive will result in the data on that drive being no
longer accessible, it is strongly advised that this feature be invoked and managed by a
system administrator. For detailed user information consult the appropriate user reference
guide for this system.
4.6.1.2 Cable Lock Provision
These systems include a chassis cutout (on the rear panel) for the attachment of a cable lock
mechanism.
4.6.1.3 I/O Interface Security
Serial, parallel, and (on iPAQ legacy systems) the USB interfaces may be disabled individually
through the Setup utility (F10) to guard against unauthorized access to a system. On iPAQ 2.0
systems the NIC interface may also be disabled through Setup.
4.6.2 POWER MANAGEMENT
The iPAQ 2.0 systems provide baseline hardware support of ACPI- and APM-compliant firmware
and software. Key power-consuming components (processor, chipset, I/O controller, and fan) can
be placed into a reduced power mode either automatically or by user control. The system can then
be brought back up ("wake-up") by events defined by the ACPI specification. The ACPI wake-up
events supported by this system are listed as follows:
ACPI Wake-Up Event System Wakes From
Power Button Suspend or soft-off
RTC Alarm Suspend or soft-off
W ake On LAN (w/NIC) Suspend or soft-off
PME Suspend or soft-off
Serial Port Ring Suspend or soft-off
USB Suspend only
Keyboard Suspend only
Mouse Suspend only
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Chapter 4 System Support
4.6.3 SYSTEM STATUS
The iPAQ 2.0 systems provide a visual indication of system boot and ROM flash status through the
keyboard LEDs as listed in table 4-8.
NOTE: The LED indications listed in Table 4-8 are valid only for PS/2-type
keyboards. A USB keyboard will not provide LED status for the listed events, although
audible (beep) indications will occur.
Table 4-8. iPAQ 2.0 System Boot/ROM Flash Status LED Indications
Table 4-8.
IPAQ 2.0 System Boot/ROM Flash Status LED Indications
NUM Lock CAPs Lock Scroll Lock
Event LED LED LED
System memory failure [1] Blinking Off Off
Graphics controller failure [2] Off Blinking Off
System failure prior to graphics cntlr. initialization [3] Off Off Blinking
ROMPAQ diskette not present, faulty, or drive prob. On Off Off
Password prompt Off On Off
Invalid ROM detected - flash failed Blinking [4] Blinking [4] Blinking [4]
Keyboard locked in network mode Blinking [5] Blinking [5] Blinking [5]
Successful boot block ROM flash On [6] On [6] On [6]
NOTES:
[1] Accompanied by 1 short, 2 long audio beeps
[2] Accompanied by 1 long, 2 short audio beeps
[3] Accompanied by 2 long, 1 short audio beeps
[4] All LEDs will blink in sync twice, accompanied by 1 long and three short audio beeps
[5] LEDs will blink in sequence (NUM Lock, then CAPs Lock, then Scroll Lock)
[6] Accompanied by rising audio tone.
Table 4-9 lists the operation status codes provided by the iPAQ 2.0 power LED on the front of the
chassis.
Table 4-9. System Status LED Indications
Table 4-9.
IPAQ 2.0 System Status LED Indications
System Status Power LED
S0: System on (normal operation) Steady green
S1: Suspend Blinks green @ 1 Hz
S3: Suspend to RAM Blinks green @ 0.5 Hz
S4: Suspend to disk Blinks green @ 0.25 Hz
S5: Soft off Off - clear
Processor not seated Steady red
CPU thermal shutdown Blinks red @ 4 Hz
ROM error Blinks red @ 1 Hz
Power supply crowbar activated Blinks red @ .5 Hz
System off Off
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Technical Reference Guide
4.6.4 TEMPERATURE SENSING AND COOLING
These systems feature a variable-speed fan integrated into the power supply assembly. Fan speed is
determined by the power supply's internal sensor.
All systems are designed to use a processor with a passive heat sink. The iPAQ 1.0/1.2 system
includes a system board connector for a processor fan, which, if present, operates in tandem with
the power supply fan. The iPAQ 2.0 system does not provide a connector for a heat sink fan and
therefore should not be upgraded with a processor using a heat sink-mounted fan (refer to
processor upgrading section 3.2.3.).
NOTE: These systems are designed to provide optimum cooling with the cover in place.
Operating a system with the cover removed may result in a thermal condition of system
board components, including the processor.
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Chapter 4 System Support
4 .7 REGISTER MAP AND MISCELLANEOUS FUNCTIONS
This section contains the system I/O map and information on general-purpose functions of the ICH
and I/O controller.
4.7.1 SYSTEM I/O MAP
Table 4-10 lists the fixed addresses of the input/output (I/O) ports.
Table 4-10. System I/O Map
Table 4-10.
System I/O Map
I/O Port Function
0000..001Fh DMA Controller 1
0020..002Dh Interrupt Controller 1
002E, 002Fh Index, Data Ports to LPC47B357 I/O Controller (primary)
0030..003Dh Interrupt Controller
0040..0042h Timer 1
004E, 004Fh Index, Data Ports to LPC47B357 I/O Controller (secondary)
0050..0052h Timer / Counter
0060..0067h Microcontroller, NMI Controller (alternating addresses)
0070..0077h RTC Controller
0080..0091h DMA Controller
0092h Port A, Fast A20/Reset Generator
0093..009Fh DMA Controller
00A0..00B1h Interrupt Controller 2
00B2h, 00B3h APM Control/Status Ports
00B4..00BDh Interrupt Controller
00C0..00DFh DMA Controller 2
00F0h Coprocessor error register
0170..0177h IDE Controller 2 (active only if standard I/O space is enabled for primary drive)
01F0..01F7h IDE Controller 1 (active only if standard I/O space is enabled for secondary drive)
0278..027Fh Parallel Port (LPT2)
02E8..02EFh Serial Port (COM4)
02F8..02FFh Serial Port (COM2)
0370..0377h Diskette Drive Controller Secondary Address
0376h IDE Controller 2 (active only if standard I/O space is enabled for primary drive)
0378..037Fh Parallel Port (LPT1)
03B0..03DFh Graphics Controller
03BC..03BEh Parallel Port (LPT3)
03E8..03EFh Serial Port (COM3)
03F0..03F5h Diskette Drive Controller Primary Addresses
03F6h IDE Controller 1 (active only if standard I/O space is enabled for sec. drive)
03F8..03FFh Serial Port (COM1)
04D0, 04D1h Interrupt Controller
0678..067Fh Parallel Port (LPT2)
0778..077Fh Parallel Port (LPT1)
07BC..07BEh Parallel Port (LPT3)
0CF8h PCI Configuration Address (dword access only )
0CF9h Reset Control Register
0CFCh PCI Configuration Data (byte, word, or dword access)
NOTE:
Assume unmarked gaps are unused, reserved, or used by functions that employ variable I/O
address mapping. Some ranges may include reserved addresses.
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4.7.2 82801 ICH GENERAL PURPOSE FUNCTIONS
The 82801 ICH2 component includes a number of single and multi-purpose pins available as
general-purpose input/output (GPIO) ports. The GPIO ports are configured (enabled/disabled)
during POST by BIOS through the PCI configuration registers of the ICH's LPC I/F Bridge
(82801, function 0). The GPIO ports are controlled through 64 bytes of I/O space that is mapped
during POST.
Table 4-11 lists the utilization of the ICH's GPIO ports.
Table 4-11. 82801 ICH GPIO Register Utilization
Table 4-11.
82801 ICH2 GPIO Register Utilization
GPIO Port # Function Direction
0 PS LED detect I
1 NIC REQ5 I
2 IRQE- I
3 IRQF- I
4 IRQG- I
5 IRQH- I
6 HD LED detect I
7 -- NC
8 -- NC
11 Multibay device detect I
12 -- NC
13 SMI from I/O I
18 -- NC
19 -- NC
20 -- NC
21 -- NC
22 -- NC
23 -- NC
24 -- NC
25 -- NC
26 -- NC
27 -- NC
28 Password (1 = Enabled, 0 = Disabled) I
NOTE:
NC = not connected (not used).
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Chapter 4 System Support
4.7.3 I/O CONTROLLER FUNCTIONS
The I/O controller contains various functions such as the keyboard/mouse interfaces, diskette
interface, serial interfaces, and parallel interface. While the control of these interfaces uses
standard AT-type I/O addressing (as described in chapter 5) the configuration of these functions
occurs through indexed ports using PnP protocol. In these systems, hardware strapping selects I/O
addresses 02Eh/02Fh at reset as the Index/Data ports for accessing the logical devices within the
I/O contoller. Table 4-12 lists the PnP control registers for the LPC47Bxx7.
Table 4-12 I/O Controller Control Registers
Table 4-12.
I/O Controller Control Registers
Index Function Reset Value
02h Configuration Control 00h
03h Reserved
07h Logical Device (Interface) Select: 00h
00h = Diskette Drive I/F
01h = Rsvd
02h = Rsvd
03h = Parallel I/F
04h = Serial I/F (UART 1)
05h = Serial I/F (UART 2)
06h = Rsvd
07h = Keyboard I/F
08h = Rsvd
09h = Rsvd
0Ah = Runtime Reg. (GPIO Config.)
0Bh = Rsvd
20h Super I/O ID Register (SID) 56H
21h Revision --
22h Logical Device Power Control 00h
23h Logical Device Power Management 00h
24h PLL / Oscillator Control 04h
25-2Fh Device specific [2] --
NOTES:
Refer to LPC47Bxx7 data sheet for detailed register information.
The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after the
configuration phase has been activated by writing 55h once to I/O port 2Eh. The BIOS then
initiates each logical device and then deactivates the configuration phase by writing AAh to 2Eh.
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Technical Reference Guide
4.7.3.1 LPC47B357 GPIO Utilization
The LPC47B357 I/O Controller (used in iPAQ 2.0 systems) provides 62 general-purpose pins that
can be individually configured for specific purposes. These pins are configured through the
Runtime registers (logical device 0Ah) during the system's configuration phase of the boot
sequence by the BIOS.
Table 4-13 lists the GPIO registers for the LPC47B357. Note that not all ports are listed as this
table defines only the custom implementation of GPIO ports. Refer to SMC documentation for
standard usage of unlisted GPIO ports.
Table 4-13. LPC47B357 GPIO Register Utilization (Desktop and Minitower only)
Table 4-13.
LPC47B357 GPIO Port Utilization (iPAQ 2.0 Only)
GPIO Function Direction GPIO Function Direction
10 Board rev 1 I 42 PME- to ICH2 O
11 Board rev 0 I 43 -- NC
12 Multibay power I 44 Hood Lock NC
13 PME- I 45 Hood Unlock NC
14 W OL NC 46 SMI- to ICH2 O
15 System ID 4 [1] I 60 PCI Slot Reset NC
16 Processor Fan sense NC 61 AGP Slot Reset NC
17 LED test O 62 PW R Button In I
20 Pri. IDE 80-pin Cable Detect I 63 SLP S3 I
21 Sec. IDE 80-pin Cable Detect I 64 SLP S5 I
22 Multibay reset O 65 CPU Changed/Removed [2] O
23 System ID 2 [1] I 66 PW R Button Out O
24 BIOS fail for AOL O 67 PS On (1 = on, 0 = off) O
25 System ID 3 [1] I 70 A20 Gate control O
26 Processor Present I 71 System ID 0 [1] NC
27 -- NC 72 System ID 1 [1] NC
30 PS LED Color Grn O 73 -- NC
31 PS LED Blink O 74 -- NC
32 Thermal Trip I 75 PW R GD (to clock chip) NC
33 2 MB Media ID NC 76 FAN OFF- O
34 FW H Write Protect O 85 Kybd/Mouse PWR O
35 FW H Reset O 86 S3 3.3 VDC On O
36 Diskette Motor B NC -- -- --
37 Diskette Select B NC -- -- --
NOTE:
NC = Not connected (not used).
[1] System ID (ID4..0) value for these systems = 00111.
[2] If set, will force "Safe Boot" mode.
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Chapter 4 System Support
4.7.3.2 LPC47B357 I/O Controller Miscellaneous Functions
The iPAQ 2.0 systems utilize the following specialized functions built into the LPC 47B357 I/O
Controller:
Power/Hard drive LED control The I/O controller provides color and blink control for the
front panel LEDs used for indicating system events as listed below:
System Status Power LED HD LED
S0: System on (normal operation) Steady green Green w/HD activity
S1: Suspend Blinks green @ 1 Hz Off
S3: Suspend to RAM Blinks green @ .5 Hz Off
S4: Suspend to disk Blinks green @ 0.25 Hz Off
S5: Soft off Off - clear Off
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