Processor not seated Steady red Off
CPU thermal shutdown Blinks red @ 4 Hz Off
ROM error Blinks red @ 1 Hz Off
Power supply crowbar activated Blinks red @ 0.5 Hz Off
System off Off Off
I/O security The parallel, serial, and diskette interfaces may be disabled individually by
software and the LPC47B357's disabling register locked. If the disabling register is locked, a
system reset through a cold boot is required to gain access to the disabling (Device Disable)
register.
Processor present/speed detection One of the battery-back general-purpose inputs (GPI26)
of the LPC47B357 detects if the processor has been removed. The occurrence of this event is
passed to the ICH that will, during the next boot sequence, initiate the speed selection routine
for the processor. The speed selection function replaces the manual DIP switch configuration
procedure required on previous systems.
Legacy/ACPI power button mode control The LPC47B357 receives the pulse signal from
the system's power button and produces the PS On signal according to the mode (legacy or
ACPI) selected. Refer to chapter 7 for more information regarding power management.
4.7.4 820802 FWH FUNCTIONS
The 82802 Firmware Hub (FWH) is loaded with Compaq BIOS, which is discussed in Chapter 7.
The FWH component also includes general purpose ports that are utilized on the iPAQ 2.0 as
indicated in the following table:
Table 4-14. 82802 FWH GPIO Register Utilization
Table 4-14.
82802 FWH GPIO Register Utilization (iPAQ 2.0 Only)
GPIO Port # Function Direction
0 Legacy module detect (0 = installed, 1 = not installed) I
1, 3, 4 Not used NC
2 Display cache module detect I
NOTE:
NC = not connected (not used).
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Chapter 5
INPUT/OUTPUT INTERFACES
5. Chapter 5 INPUT/OUTPUT INTERFACES
5 .1 INTRODUCTION
This chapter describes the standard (i.e., system board) interfaces that provide input and output
(I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped
registers. The following I/O interfaces are covered in this chapter:
Enhanced IDE interface (5.2) page 5-1
Diskette drive interface (5.3) page 5-5
Serial interfaces (5.4) page 5-6
Parallel interface (5.5) page 5-9
Keyboard/pointing device interface (5.6) page 5-15
Universal serial bus interface (5.7) page 5-22
Audio subsystem (5.8) page 5-26
Network support (5.9) page 5-32
5 .2 ENHANCED IDE INTERFACE
The enhanced IDE (EIDE) interface consists of primary and secondary controllers integrated into
the 82801 component of the chipset. The primary IDE controller supports the hard drive while the
secondary controller supports a device installed in the Multibay. Each controller can be configured
independently for the following modes of operation:
Programmed I/O (PIO) mode CPU controls drive transactions through standard I/O mapped
registers of the IDE drive.
8237 DMA mode CPU offloads drive transactions using DMA protocol with transfer rates
up to 16 MB/s.
Ultra ATA/66 and UATA/100 modes Preferred bus mastering source-synchronous protocol
providing peak transfer rates of 66 MB/s (iPAQ 1.x) and 100 MB/s (iPAQ 2.0).
5.2.1 IDE PROGRAMMING
The IDE interface is configured as a PCI device during POST and controlled through I/O-mapped
registers at runtime. Hard drives types not found in the ROM's parameter table are automatically
configured as to (soft)type by DOS as follows:
Primary controller: drive 0, type 65; drive 1, type 66
Secondary controller: drive 0, type 68; drive 1, type 15
Non-DOS (non-Windows) operating systems may require using Setup (F10) for drive
configuration.
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Chapter 5 Input/Output Interfaces
5.2.1.1 IDE Configuration Registers
The IDE controller is configured as a PCI device with bus mastering capability. The PCI
configuration registers for the IDE controller function (PCI device #31, function #1) are listed in
Table 5-1.
Table 51. IDE PCI Configuration Registers
Table 5-1.
EIDE PCI Configuration Registers (82801, Device 31/Function 1)
PCI Conf. Reset PCI Conf. Reset
Addr. Register Value Addr. Register Value
00-01h Vender ID 8086h 24-2Bh Reserved 0's
02-03h Device ID [1] 2C, 2Dh Subsystem Vender ID 8086h
04-05h PCI Command 0000h 2E, 2Fh Subsystem ID 2411h
06-07h PCI Status 0280h 30-3Fh Reserved 0's
08h Revision ID 00h 40-43h Primary IDE Timing 0000h
09h Programming 80h 44h Secondary IDE Timing 00h
0Ah Sub-Class 01h 48h Sync. DMA Control 00h
0Bh Base Class Code 01h 4A-4Bh Sync. DMA Timing 0000h
0Dh Master Latency Timer 0000h 54h EIDE I/O Config.Register 00h
0Eh Header Type 80h F8-FBh Manufacturer's ID
0F-1Fh Reserved 00h FC-FFh Reserved
20-23h BMIDE Base Address 1h -- -- --
NOTE:
Assume unmarked gaps are reserved and/or not used.
[1] 82801AA ICH = 2411h, 82801BA ICH2 = 244Bh
5.2.1.2 IDE Bus Master Control Registers
The IDE interface can perform PCI bus master operations using the registers listed in Table 5-2.
These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI
configuration register 20h in the previous table.
Table 52. IDE Bus Master Control Registers
Table 5-2.
IDE Bus Master Control Registers
I/O Addr. Size Default
Offset (Bytes) Register Value
00h 1 Bus Master IDE Command (Primary) 00h
02h 1 Bus Master IDE Status (Primary) 00h
04h 4 Bus Master IDE Descriptor Pointer (Pri.) 0000 0000h
08h 1 Bus Master IDE Command (Secondary) 00h
0Ah 2 Bus Master IDE Status (Secondary) 00h
0Ch 4 Bus Master IDE Descriptor Pointer (Sec.) 0000 0000h
NOTE:
Unspecified gaps are reserved, will return indeterminate data, and should not be written to.
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5.2.2 PRIMARY IDE INTERFACE
These systems use a standard 40-pin connector for the primary IDE device that connects (via a
cable) to the hard drive installed in the drive bay. Note that some signals are re-defined for
UATA/33, /66, and /100 modes, which require a special 80-conductor cable (supplied) designed to
reduce cross-talk. Device power is supplied through a separate connector.
Figure 5-1. 40-Pin Primary IDE Connector (on system board).
Table 53. 40-Pin Primary IDE Connector Pinout
Table 5-3.
40-Pin Primary IDE Connector Pinout
Pin Signal Description Pin Signal Description
1 RESET- Reset 21 DRQ DMA Request
2 GND Ground 22 GND Ground
3 DD7 Data Bit <7> 23 IOW - I/O Write [1]
4 DD8 Data Bit <8> 24 GND Ground
5 DD6 Data Bit <6> 25 IOR- I/O Read [2]
6 DD9 Data Bit <9> 26 GND Ground
7 DD5 Data Bit <5> 27 IORDY I/O Channel Ready [3]
8 DD10 Data Bit <10> 28 CSEL Cable Select
9 DD4 Data Bit <4> 29 DAK- DMA Acknowledge
10 DD11 Data Bit <11> 30 GND Ground
11 DD3 Data Bit <3> 31 IRQn Interrupt Request [4]
12 DD12 Data Bit <12> 32 IO16- 16-bit I/O
13 DD2 Data Bit <2> 33 DA1 Address 1
14 DD13 Data Bit <13> 34 DSKPDIAG Pass Diagnostics
15 DD1 Data Bit <1> 35 DA0 Address 0
16 DD14 Data Bit <14> 36 DA2 Address 2
17 DD0 Data Bit <0> 37 CS0- Chip Select
18 DD15 Data Bit <15> 38 CS1- Chip Select
19 GND Ground 39 HDACTIVE- Drive Active (front panel LED) [5]
20 -- Key 40 GND Ground
NOTES:
[1] On UATA/33, /66, and /100 modes, re-defined as STOP.
[2] On UATA/33, /66 and /100 mode reads, re-defined as DMARDY-.
On UATA/33, /66 and /100 mode writes, re-defined as STROBE.
[3] On UATA/33, /66 and /100 mode reads, re-defined as STROBE-.
On UATA/33, /66 and /100 mode writes, re-defined as DMARDY-.
[4] Primary connector wired to IRQ14, secondary connector wired to IRQ15.
[5] Pin 39 is used for spindle sync and drive activity (becomes SPSYNC/DACT-)
when synchronous drives are connected.
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Chapter 5 Input/Output Interfaces
5.2.3 SECONDARY IDE INTERFACE
The secondary IDE interface supports the Multibay device, which may be an optical storage device
(CD-ROM, DVD, LS-120) or a second hard drive mounted in a Multibay adapter that in turn is
installed in the Multibay. Both iPAQ 1.x and 2.0 systems provide a 68-pin female connector
(mounted on a Multibay board) that mates with the corresponding male connector of the Multibay
device or adapter.
1
Figure 5-2. 68-Pin Multibay Connector (on Multibay board).
Table 54. 68-Pin Multibay Connector Pinout
Table 5-4.
68-Pin Multibay Connector Pinout
Pin Signal Description Pin Signal Description
1 RST- Reset 2 GND Ground
3 DD7 Drive Data Bit <7> 4 DD8 Drive Data Bit <8>
5 DD6 Drive Data Bit <6> 6 DD9 Drive Data Bit <9>
7 DD5 Drive Data Bit <5> 8 DD10 Drive Data Bit <10>
9 DD4 Drive Data Bit <4> 10 DD11 Drive Data Bit <11>
11 DD3 Drive Data Bit <3> 12 DD12 Drive Data Bit <12>
13 DD2 Drive Data Bit <2> 14 DD13 Drive Data Bit <13>
15 DD1 Drive Data Bit <1> 16 DD14 Drive Data Bit <14>
17 DD0 Drive Data Bit <0> 18 DD15 Drive Data Bit <15>
19 GND Ground 20 (key) No connection
21 DREQ DMA request 22 GND Ground
23 IOW Drive I/O Write 24 GND Ground
25 IOR Drive I/O Read 26 GND Ground
27 IORDY I/O Channel Ready 28 CSEL Cable select
29 DACK DMA Acknowledge 30 GND Ground
31 IRQ Interrupt request 32 GND Ground
33 DA1 Drive address bit <1> 34 PDIAG Passed diagnostics
35 DA0 Drive address bit <0> 36 DA2 Drive address bit <2>
37 CS1 Chip select 1 38 CS3 Chip select 3
39 DASP- Drive activity/drive 1 prsnt. 40 GND Ground
41 Vc c +5 VDC logic power 42 MTR PWR +5 VDC motor power
43 GND Ground 44 AUD L Left audio
45 GND Left audio ground 46 GND Right audio ground
47 AUD R Right audio 48 INDEX- Index
49 Vcc +5 VDC 50 DRVSEL Drive select
51 DSKCHG Disk change 52 GND Ground
53 DEN ID Media identification 54 MTR ON- Motor On
55 LOW DEN- Density select 56 DIR- Direction in
57 STEP- Step 58 DEV PRST System device present
59 W DATA- W rite data 60 GND Ground
61 W GATE- W rite gate 62 TRK0- Track 00
63 GND Ground 64 W PROT- W rite protect
65 GND Ground 66 RDATA- Read data
67 GND Ground 68 HDSEL- Head (side one) select
Diskette drive interface not connected.
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5 .3 DISKETTE DRIVE INTERFACE
NOTE: The Compaq iPAQ does not support a diskette drive. However, the I/O
controller component contains a diskette drive controller that may need to be enabled
(though Setup) to satisfy the requirements of some operating systems. This may result in
device manager applications indicating the presence of a diskette drive that in fact is not
available.
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Chapter 5 Input/Output Interfaces
5.4 SERIAL INTERFACE
The legacy models include a serial interface to transmit and receive asynchronous serial data with
external devices. The serial interface function is provided by the I/O controller component that
includes a NS16C550-compatible UART.
NOTE: Legacy-free models do not have an externally accessible serial port, but do have
serial interface logic to satisfy the serial port requirements of some operating systems.
The iPAQ2.0 and legacy-free iPAQ 1.x systems also includes a serial test header on the
system board.
The UART supports the standard baud rates up through 115200, and also special high speed rates
of 239400 and 460800 baud. The baud rate of the UART is typically set to match the capability of
the connected device. While most baud rates may be set at runtime, baud rates 230400 and
460800 must be set during the configuration phase.
5.4.1 RS-232 INTERFACE
On the legacy system, the UART is associated with a DB-9 connector that complies with EIA
standard RS-232-C. The DB-9 connector is shown in the following figure and the pinout of the
connector is listed in Table 5-5.
Figure 5-3. Serial Interface Connector (Male DB-9 as viewed from rear of chassis)
Table 55. DB-9 Serial Connector Pinout
Table 5-5.
DB-9 Serial Connector Pinout
Pin Signal Description Pin Signal Description
1 CD Carrier Detect 6 DSR Data Set Ready
2 RX Data Receive Data 7 RTS Request To Send
3 TX Data Transmit Data 8 CTS Clear To Send
4 DTR Data Terminal Ready 9 RI Ring Indicator
5 GND Ground -- -- --
The standard RS-232-C limitation of 50 feet (or less) of cable between the DTE (computer) and
DCE (modem) should be followed to minimize transmission errors. Higher baud rates may require
shorter cables.
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5.4.2 SERIAL TEST INTERFACE
iPAQ 1.x legacy-free and iPAQ 2.0 systems include a serial header connector on the system board
to satisfy the requirements of some operating systems. The test header and pinout is shown in the
following figure:
CD 1 2 DSR
RX Data 3 4 RTS
TX Data 5 6 CTS
DTR 7 8 RI
Gnd 9
Figure 5-4. Serial Interface Header (iPAQ 1.2 legacy-free and 2.0 system boards only)
5.4.3 SERIAL INTERFACE PROGRAMMING
Programming the serial interfaces consists of configuration, which occurs during POST, and
control, which occurs during runtime.
5.4.3.1 Serial Interface Configuration
The serial interface must be configured for a specific address range (COM1, COM2, etc.) and also
must be activated before it can be used. Address selection and activation of the serial interface are
affected through the PnP configuration registers of the LPC47B277 I/O controller.
The serial interface configuration registers are listed in the following table:
Table 56. Serial Interface Configuration Registers
Table 5-6.
Serial Interface Configuration Registers
Index
Address Function R/W
30h Activate R/W
60h Base Address MSB R/W
61h Base Address LSB R/W
70h Interrupt Select R/W
F0h Mode Register R/W
NOTE:
Refer to LPC47B277 data sheet for detailed register information.
5.4.3.2 Serial Interface Control
The BIOS function INT 14 provides basic control of the serial interface. The serial interface can
be directly controlled by software through the I/O-mapped registers listed in Table 5-7.
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Chapter 5 Input/Output Interfaces
Table 57. Serial Interface Control Registers
Table 5-7.
Serial Interface Control Registers
COM1 COM2
Addr. Addr. Register R/W
3F8h 2F8h Receive Data Buffer R
Transmit Data Buffer W
Baud Rate Divisor Register 0 (when bit 7 of Line Control Reg. Is set) W
3F9h 2F9h Baud Rate Divisor Register 1 (when bit 7 of Line Control Reg. Is set) W
Interrupt Enable Register: R/W
<7..4> Reserved (always 0's)
<3> Modem status interrupt enable (active high) (CTS, DSR, RI, CD)
<2> Rx line status interrupt enable (active high) (Overrun, parity, framing error)
<1> Tx holding register empty interrupt enable (active high)
<0> Baud rate divisor interrupt enable (active high)
3FAh 2FAh Interrupt ID Register: R
<7,6> FIFO Enable/Disable: 0 = disable, 1 = enable
<5,4> Reserved
<3..1> Interrupt Source:
000 = Modem status 100,101 = Reserved
001 = TX holding reg. Empty 110 = Character time-out
010 = RX data available 111 = Reserved
011 = RX line status
<0> Interrupt pending (if cleared)
FIFO Control Register: W
<7,6> RX Trigger Level: 00 = 1 byte, 01 = 4 bytes, 10 = 8 bytes, 11 = 14 bytes
<5..3> Rerserved
<2> TX FIFO reset (active high)
<1> RX FIFO reset (active high)
<0> FIFO Enable/Disable: 0 = Disable TX/RX FIFO's, 1 = Enable TX/RX FIFO's
3FBh 2FBh Line Control Register: R/W
<7> Register acces control:
0 = RX buffer, TX holding, divisor rate registers are accessable.
1 = Divisor rate register is accessable
<6> Break control (forces SOUT singla low if set)
<5> Stick parity (if set, even parity bit is 0, odd parity bit is 1)
<4> Parity type: 0 = odd, 1 = even
<3> Parity enable: 0 = disabled, 1 = enabled
<2> Stop bit: 0 = 1 stop bit, 1 = 2 stop bits
<1,0> Word size: 00 = 5 bits, 01 = 6 bits, 10 = 7 bits, 11 = 8 bits
3FCh 2FCh Modem Control Register: R/W
<7..5> Reserved
<4> Internal loopback enabled (if set)
<3> Serial I/F interrupts enabled (if set)
<2> Reserved
<1> RTS signal active (if set)
<0> DTR signal active (if set)
3FDh 2FDh Line Status Register: R
<7> Parity error, framing error, or Break condition (if set)
<6> TX holding and TX shift registers are empty (if set)
<5> TX holding register is empty (if set)
<4> Break interrupt has occurred (if set)
<3> Framing error has occurred (if set)
<2> Parity error has occurred (if set)
<1> Overrun error has occurred (if set)
<0> Data register ready to be read (if set)
3FEh 2FEh Modem Status: R
<7..4> DCD-, RI-, DSR, CTS (respectively) active (if set)
<3..0> DCD-, RI-, DSR, CTS (respectively) changed state since last read (if set)
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5.5 PARALLEL INTERFACE
The legacy models include a parallel interface for connection to a peripheral device that has a
compatible interface, the most common being a printer. The parallel interface function is integrated
into the I/O controller component and provides bi-directional 8-bit parallel data transfers with a
peripheral device. The parallel interface supports three main modes of operation:
Standard Parallel Port (SPP) mode
Enhanced Parallel Port (EPP) mode
Extended Capabilities Port (ECP) mode
These three modes (and their submodes) provide complete support as specified for an IEEE 1284
parallel port.
5.5.1 STANDARD PARALLEL PORT MODE
The Standard Parallel Port (SPP) mode uses software-based protocol and includes two sub-modes
of operation, compatible and extended, both of which can provide data transfers up to 150 KB/s. In
the compatible mode, CPU write data is simply presented on the eight data lines. A CPU read of
the parallel port yields the last data byte that was written. The following steps define the standard
procedure for communicating with a printing device:
1. The system checks the Printer Status register. If the Busy, Paper Out, or Printer Fault signals
are indicated as being active, the system either waits for a status change or generates an error
message.
2. The system sends a byte of data to the Printer Data register, then pulses the printer STROBE
signal (through the Printer Control register) for at least 500 ns.
3. The system then monitors the Printer Status register for acknowledgment of the data byte
before sending the next byte.
In extended mode, a direction control bit (CTR 37Ah, bit <5>) controls the latching of output data
while allowing a CPU read to fetch data present on the data lines, thereby providing bi-directional
parallel transfers to occur. The SPP mode uses three registers for operation: the Data register
(DTR), the Status register (STR) and the Control register (CTR). Address decoding in SPP mode
includes address lines A0 and A1.
5.5.2 ENHANCED PARALLEL PORT MODE
In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due to
a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7 and
1.9 are both supported. For the parallel interface to be initialized for EPP mode, a negotiation
phase is entered to detect whether or not the connected peripheral is compatible with EPP mode. If
compatible, then EPP mode can be used. In EPP mode, system timing is closely coupled to EPP
timing. A watchdog timer is used to prevent system lockup. Five additional registers are available
in EPP mode to handle 16- and 32-bit CPU accesses with the parallel interface. Address decoding
includes address lines A0, A1, and A2.
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Chapter 5 Input/Output Interfaces
5.5.3 EXTENDED CAPABILITIES PORT MODE
The Extended Capabilities Port (ECP) mode, like EPP, also uses a hardware protocol-based design
that supports transfers up to 2 MB/s. Automatic generation of addresses and strobes as well as Run
Length Encoding (RLE) decompression is supported by ECP mode. The ECP mode includes a bi-
directional FIFO buffer that can be accessed by the CPU using DMA or programmed I/O. For the
parallel interface to be initialized for ECP mode, a negotiation phase is entered to detect whether
or not the connected peripheral is compatible with ECP mode. If compatible, then ECP mode can
be used.
Ten control registers are available in ECP mode to handle transfer operations. In accessing the
control registers, the base address is determined by address lines A2-A9, with lines A0, A1, and
A10 defining the offset address of the control register. Registers used for FIFO operations are
accessed at their base address + 400h (i.e., if configured for LPT1, then 378h + 400h = 778h).
The ECP mode includes several sub-modes as determined by the Extended Control register. Two
submodes of ECP allow the parallel port to be controlled by software. In these modes, the FIFO is
cleared and not used, and DMA and RLE are inhibited.
5.5.4 PARALLEL INTERFACE PROGRAMMING
Programming the parallel interface consists of configuration, which typically occurs during POST,
and control, which occurs during runtime.
5.5.4.1 Parallel Interface Configuration
The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and also
must be enabled before it can be used. When configured for EPP or ECP mode, additional
considerations must be taken into account. Address selection, enabling, and EPP/ECP mode
parameters of the parallel interface are affected through the PnP configuration registers of the
LPC47B347 I/O controller. Address selection and enabling are automatically done by the BIOS
during POST but can also be accomplished with the Setup utility and other software.
The parallel interface configuration registers are listed in the following table:
Table 58. Parallel Interface Configuration Registers
Table 5-8.
Parallel Interface Configuration Registers
Index Reset
Address Function R/W Value
30h Activate R/W 00h
60h Base Address MSB R/W 00h
61h Base Address LSB R/W 00h
70h Interrupt Select R/W 00h
74h DMA Channel Select R/W 04h
F0h Mode Register R/W 00h
F1h Mode Register 2 R/W 00h
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5.5.4.2 Parallel Interface Control
The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions
such as initialization, character printing, and printer status are provide by subfunctions of INT 17.
The parallel interface is controllable by software through a set of I/O mapped registers. The
number and type of registers available depends on the mode used (SPP, EPP, or ECP). Table 5-9
lists the parallel registers and associated functions based on mode.
Table 59. Parallel Interface Control Registers
Table 5-9.
Parallel Interface Control Registers
ECP
EPP
I/O SPP
M ode
M ode
Address Register M ode
Ports
Ports
Ports
Base Data LPT1,2,3 LPT1,2 LPT1,2,3
Base + 1h Printer Status LPT1,2,3 LPT1,2 LPT1,2,3
Base + 2h Control LPT1,2,3 LPT1,2 LPT1,2,3
Base + 3h Address -- LPT1,2 --
Base + 4h Data Port 0 -- LPT1,2 --
Base + 5h Data Port 1 -- LPT1,2 --
Base + 6h Data Port 2 -- LPT1,2 --
Base + 7h Data Port 3 -- LPT1,2 --
Base + 400h Parallel Data FIFO -- -- LPT1,2,3
Base + 400h ECP Data FIFO -- -- LPT1,2,3
Base + 400h Test FIFO -- -- LPT1,2,3
Base + 400h Configuration Register A -- -- LPT1,2,3
Base + 401h Configuration Register B -- -- LPT1,2,3
Base + 402h Extended Control Register -- -- LPT1,2,3
Base Address:
LPT1 = 378h
LPT2 = 278h
LPT3 = 3BCh
The following paragraphs describe the individual registers. Note that only the LPT1-based
addresses are given in these descriptions.
Data Register, I/O Port 378h
Data written to this register is presented to the data lines D0-D7. A read of this register when in
SPP-compatible mode yields the last byte written. A read while in SPP-extended or ECP mode
yields the status of data lines D0-D7 (i.e., receive data).
In ECP mode in the forward (output) direction, a write to this location places a tagged command
byte into the FIFO and reads have no effect.
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Status Register, I/O Port 379h, Read Only
This register contains the current printer status. Reading this register clears the interrupt condition
of the parallel port.
Bit Function
7 Printer Busy (if 0)
6 Printer Acknowledgment Of Data Byte (if 0)
5 Printer Out Of Paper (if 1)
4 Printer Selected/Online (if 1)
3 Printer Error (if 0)
2 Reserved
1 EPP Interrupt Occurred (if set while in EPP mode)
0 EPP Timeout Occurred (if set while in EPP mode)
Control Register, I/O Port 37Ah
This register provides the printer control functions.
Bit Function
7,6 Reserved
5 Direction Control for PS/2 and ECP Modes:
0 = Forward. Drivers enabled. Port writes to peripheral (default)
1 = Backward. Tristates drivers and data is read from peripheral
4 Acknowledge Interrupt Enable
0 = Disable ACK interrupt
1 = Enable interrupt on rising edge of ACK
3 Printer Select (if 0)
2 Printer Initialize (if 1)
1 Printer Auto Line Feed (if 0)
0 Printer Strobe (if 0)
Address Register, I/O Port 37Bh (EPP Mode Only)
This register is used for selecting the EPP register to be accessed.
Data Port Registers 0-3, I/O Ports 37C-Fh (EPP Mode Only)
These registers are used for reading/writing data. Port 0 is used for all transfers. Ports 1-3 are used
for transferring the additional bytes of 16- or 32-bit transfers through port 0.
FIFO Register, I/O Port 7F8h (ECP Mode Only)
While in ECP/forward mode, this location is used for filling the 16-byte FIFO with data bytes.
Reads have no effect (except when used in Test mode). While in ECP/backward mode, reads
yield data bytes from the FIFO.
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Configuration Register A, I/O Port 7F8h (ECP Mode Only)
A read of this location yields 10h, while writes have no effect.
Configuration Register B, I/O Port 7F9h (ECP Mode, Read Only)
A read of this location yields the status defined as follows:
Bit Function
7 Reserved (always 0)
6 Status of Selected IRQn.
5,4 Selected IRQ Indicator:
00 = IRQ7
11 = IRQ5
All other values invalid.
3 Reserved (always 1)
2..0 Reserved (always 000)
Extended Control Register B, I/O Port 7FAh (ECP ModeOnly)
This register defines the ECP mode functions.
Bit Function
7..5 ECP Submode Select:
000 = Standard forward mode (37Ah <5> forced to 0). Writes are
controlled by software and FIFO is reset.
001 = PS/2 mode. Reads and writes are software controlled and
FIFO is reset.
010 = Parallel Port FIFO forward mode (37Ah <5> forced to 0). Writes
are
hardware controlled.
011 = ECP FIFO mode. Direction determined by 37Ah, <5>. Reads and
writes are hardware controlled.
4 ECP Interrupt Mask:
0 = Interrupt is generated on ERR- assertion.
1 = Interrupt is inhibited.
3 ECP DMA Enable/Disable.
0 = Disabled
1 = Enabled
2 ECP Interrupt Generation with DMA
0 = Enabled
1 = Disabled
1 FIFO Full Status (Read Only)
0 = Not full (at least 1 empty byte)
1 = Full
0 FIFO Empty Status (Read Only)
0 = Not empty (contains at least 1 byte)
1 = Empty
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Chapter 5 Input/Output Interfaces
5.5.5 PARALLEL INTERFACE CONNECTOR
Figure 5-5 and Table 5-10 show the connector and pinout of the parallel interface connector. Note
that some signals are redefined depending on the port's operational mode.
4
13 12 11 10 9 8 7 6 5 3 2 1
25 24 23 22 21 20 19 18 17 16 15 14
Figure 5-5. Parallel Interface Connector (Female DB-25 as viewed from rear of chassis)
Table 510. DB-25 Parallel Connector Pinout
Table 5-10.
DB-25 Parallel Connector Pinout
Pin S ignal Function Pin S ignal Function
1 STB- Strobe / Write [1] 14 LF- Line Feed [2]
2 D0 Data 0 15 ERR- Error [3]
3 D1 Data 1 16 INIT- Initialize Paper [4]
4 D2 Data 2 17 SLCTIN- Select In / Address. Strobe [1]
5 D3 Data 3 18 GND Ground
6 D4 Data 4 19 GND Ground
7 D5 Data 5 20 GND Ground
8 D6 Data 6 21 GND Ground
9 D7 Data 7 22 GND Ground
10 ACK- Acknowledge / Interrupt [1] 23 GND Ground
11 BSY Busy / Wait [1] 24 GND Ground
12 PE Paper End / User defined [1] 25 GND Ground
13 SLCT Select / User defined [1] -- -- --
NOTES:
[1] Standard and ECP mode function / EPP mode function
[2] EPP mode function: Data Strobe
ECP modes: Auto Feed or Host Acknowledge
[3] EPP mode: user defined
ECP modes:Fault or Peripheral Req.
[4] EPP mode: Reset
ECP modes: Initialize or Reverse Req.
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5 .6 KEYBOARD/POINTING DEVICE INTERFACE
The legacy models include PS/2-type keyboard/pointing device interfaces for the connection of a
standard enhanced keyboard and a mouse. (Legacy-free models use USB ports for keyboard/mouse
connections.) The keyboard/pointing device interface function is provided by the I/O controller
component, which integrates 8042-compatible keyboard controller logic (hereafter referred to as
simply the "8042") to communicate with the keyboard and pointing device using bi-directional
serial data transfers. The 8042 handles scan code translation and password lock protection for the
keyboard as well as communications with the pointing device. This section describes the interface
itself. The keyboard is discussed in the Appendix C.
5.6.1 KEYBOARD INTERFACE OPERATION
The data/clock link between the 8042 and the keyboard is uni-directional for Keyboard Mode 1
and bi-directional for Keyboard Modes 2 and 3. (These modes are discussed in detail in Appendix
C). This section describes Mode 2 (the default) mode of operation.
Communication between the keyboard and the 8042 consists of commands (originated by either
the keyboard or the 8042) and scan codes from the keyboard. A command can request an action or
indicate status. The keyboard interface uses IRQ1 to get the attention of the CPU.
The 8042 can send a command to the keyboard at any time. When the 8042 wants to send a
command, the 8042 clamps the clock signal from the keyboard for a minimum of 60 us. If the
keyboard is transmitting data at that time, the transmission is allowed to finish. When the 8042 is
ready to transmit to the keyboard, the 8042 pulls the data line low, causing the keyboard to
respond by pulling the clock line low as well, allowing the start bit to be clocked out of the 8042.
The data is then transferred serially, LSb first, to the keyboard (Figure 5-6). An odd parity bit is
sent following the eighth data bit. After the parity bit is received, the keyboard pulls the data line
low and clocks this condition to the 8042. When the keyboard receives the stop bit, the clock line
is pulled low to inhibit the keyboard and allow it to process the data.
D1 D2 D3 D4 D5 D6 Parity
Start D0 D7 Stop
Bit (LSb) (MSb) Bit
0 1 0 1 1 0 1 1 1 1 0
Data
Clock
Tc y Tc l Tc h Ts s Ts h
Th
Parameter Minimum Maximum
Tcy (Cycle Time) 0 us 80 us
Tcl (Clock Low) 25 us 35 us
Tch (Clock High) 25 us 45 us
Th (Data Hold) 0 us 25 us
Tss (Stop Bit Setup) 8 us 20 us
Tsh (Stop Bit Hold) 15 us 25 us
Figure 5-6. 8042-To-Keyboard Transmission of Code EDh, Timing Diagram
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Chapter 5 Input/Output Interfaces
Control of the data and clock signals is shared by the 8042and the keyboard depending on the
originator of the transferred data. Note that the clock signal is always generated by the keyboard.
After the keyboard receives a command from the 8042, the keyboard returns an ACK code. If a
parity error or timeout occurs, a Resend command is sent to the 8042. Table 5-11 lists and
describes commands that can be issued by the 8042 to the keyboard.
Table 511. 8042-To-Keyboard Commands
Table 5-11.
8042-To-Keyboard Commands
Command Value Description
Set/Reset Status Indicators EDh Enables LED indicators. Value EDh is followed by an
option byte that specifies the indicator as follows:
Bits <7..3> not used
Bit <2>, Caps Lock (0 = off, 1 = on)
Bit <1>, NUM Lock (0 = off, 1 = on)
Bit <0>, Scroll Lock (0 = off, 1 = on)
Echo EEh Keyboard returns EEh when previously enabled.
Invalid Command EFh/F1 These commands are not acknowledged.
h
Select Alternate Scan Codes F0h Instructs the keyboard to select another set of scan codes
and sends an option byte after ACK is received:
01h = Mode 1
02h = Mode 2
03h = Mode 3
Read ID F2h Instructs the keyboard to stop scanning and return two
keyboard ID bytes.
Set Typematic Rate/Display F3h Instructs the keyboard to change typematic rate and delay
to specified values:
Bit <7>, Reserved - 0
Bits <6,5>, Delay Time
00 = 250 ms
01 = 500 ms
10 = 750 ms
11 = 1000 ms
Bits <4..0>, Transmission Rate:
00000 = 30.0 ms
00001 = 26.6 ms
00010 = 24.0 ms
00011 = 21.8 ms
:
11111 = 2.0 ms
Enable F4h Instructs keyboard to clear output buffer and last
typematic key and begin key scanning.
Default Disable F5h Resets keyboard to power-on default state and halts
scanning pending next 8042 command.
Set Default F6h Resets keyboard to power-on default state and enable
scanning.
Set Keys - Typematic F7h Clears keyboard buffer and sets default scan code set. [1]
Set Keys - Make/Brake F8h Clears keyboard buffer and sets default scan code set. [1]
Set Keys - Make F9h Clears keyboard buffer and sets default scan code set. [1]
Set Keys - Typematic/Make/Brake FA h Clears keyboard buffer and sets default scan code set. [1]
Set Type Key - Typematic FBh Clears keyboard buffer and prepares to receive key ID. [1]
Set Type Key - Make/Brake FCh Clears keyboard buffer and prepares to receive key ID. [1]
Set Type Key - Make FDh Clears keyboard buffer and prepares to receive key ID. [1]
Resend FEh 8042 detected error in keyboard transmission.
Reset FFh Resets program, runs keyboard BAT, defaults to Mode 2.
Note:
[1] Used in Mode 3 only.
5-16 Compaq iPAQ Series of Desktop Personal Computers
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Technical Reference Guide
5.6.2 POINTING DEVICE INTERFACE OPERATION
The pointing device (typically a mouse) connects to a 6-pin DIN-type connector that is identical to
the keyboard connector both physically and electrically. The operation of the interface (clock and
data signal control) is the same as for the keyboard. The pointing device interface uses the IRQ12
interrupt.
5.6.3 KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING
Programming the keyboard interface consists of configuration, which occurs during POST, and
control, which occurs during runtime.
5.6.3.1 8042 Configuration
The keyboard/pointing device interface must be enabled and configured for a particular speed
before it can be used. Enabling and speed parameters of the 8042 logic are affected through the
PnP configuration registers of the LPC47B347 I/O controller. Enabling and speed control are
automatically set by the BIOS during POST but can also be accomplished with the Setup utility
and other software.
The keyboard interface configuration registers are listed in the following table:
Table 512. Keyboard Interface Configuration Registers
Table 5-12.
Keyboard Interface Configuration Registers
Index
Address Function R/W
30h Activate R/W
70h Primary Interrupt Select R/W
72h Secondary Interrupt Select R/W
F0h Reset and A20 Select R/W
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5.6.3.2 8042 Control
The BIOS function INT 16 is typically used for controlling interaction with the keyboard. Sub-
functions of INT 16 conduct the basic routines of handling keyboard data (i.e., translating the
keyboard's scan codes into ASCII codes). The keyboard/pointing device interface is accessed by
the CPU through I/O mapped ports 60h and 64h, which provide the following functions:
Output buffer reads
Input buffer writes
Status reads
Command writes
Ports 60h and 64h can be accessed using the IN instruction for a read and the OUT instruction for
a write. Prior to reading data from port 60h, the "Output Buffer Full" status bit (64h, bit <0>)
should be checked to ensure data is available. Likewise, before writing a command or data, the
"Input Buffer Empty" status bit (64h, bit <1>) should also be checked to ensure space is available.
I/O Port 60h
I/O port 60h is used for accessing the input and output buffers. This register is used to send and
receive data from the keyboard and the pointing device. This register is also used to send the
second byte of multi-byte commands to the 8042 and to receive responses from the 8042 for
commands that require a response.
A read of 60h by the CPU yields the byte held in the output buffer. The output buffer holds data
that has been received from the keyboard and is to be transferred to the system.
A CPU write to 60h places a data byte in the input byte buffer and sets the CMD/ DATA bit of the
Status register to DATA. The input buffer is used for transferring data from the system to the
keyboard. All data written to this port by the CPU will be transferred to the keyboard except bytes
that follow a multibyte command that was written to 64h
I/O Port 64h
I/O port 64h is used for reading the status register and for writing commands. A read of 64h by the
CPU will yield the status byte defined as follows:
Bit Function
7..4 General Purpose Flags.
3 CMD/DATA Flag (reflects the state of A2 during a CPU
write).
0 = Data
1 = Command
2 General Purpose Flag.
1 Input Buffer Full. Set (to 1) upon a CPU write. Cleared by
IN A, DBB instruction.
0 Output Buffer Full (if set). Cleared by a CPU read of the
buffer.
A CPU write to I/O port 64h places a command value into the input buffer and sets the
CMD/DATA bit of the status register (bit <3>) to CMD.
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Table 5-13 lists the commands that can be sent to the 8042 by the CPU. The 8042 uses IRQ1 for
gaining the attention of the CPU.
Table 513. CPU Commands To The 8042
Table 5-13.
CPU Commands To The 8042
Value Command Description
20h Put current command byte in port 60h.
60h Load new command byte. This is a two-byte operation described as follows:
1. Write 60h to port 64h.
2. Write the command byte to port 60h as follows:
Bit <7> Reserved
<6> Keyboard Code Conversion
0 = Do not convert codes
1 = Convert codes to 9-bit 8088/8086-compatible format
Bit <5> Pointing Device Enable
0 = Enable pointing device
1 = Disable pointing device
Bit <4> Keyboard Enable
0 = Enable keyboard
1 = Disable keyboard
Bit <3> Reserved
Bit <2> System Flag
0 = Cold boot
1 = CPU reset (exit from protected mode)
Bit <1> Pointing Device Interrupt Enable
0 = Disable interrupt
1 = Enable interrupt
Bit <0> Keyboard Interrupt Enable
0 = Disable interrupt
1 = Enable interrupt
A4h Test password installed. Tests whether or not a password is installed in the 8042:
If FAh is returned, password is installed.
If F1h is returned, no password is installed.
A5h Load password. This multi-byte operation places a password in the 8042 using the following
manner:
1. Write A5h to port 64h.
2. Write each character of the password in 9-bit scan code (translated) format to port 60h.
3. Write 00h to port 60h.
A6h Enable security. This command places the 8042 in password lock mode following the A5h
command. The correct password must then be entered before further communication with the 8042
is allowed.
A7h Disable pointing device. This command sets bit <5> of the 8042 command byte, pulling the clock
line of the pointing device interface low.
A8h Enable pointing device. This command clears bit <5> of the 8042 command byte, activating the
clock line of the pointing device interface.
A9h Test the clock and data lines of the pointing device interface and place test results in the output
buffer.
00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high
AAh Initialization. This command causes the 8042 to inhibit the keyboard and pointing device and
places 55h into the output buffer.
Continued
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Chapter 5 Input/Output Interfaces
Table 5-13. CPU Commands To The 8042 (Continued)
Value Command Description
ABh Test the clock and data lines of the keyboard interface and place test results in the output buffer.
00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high
ADh Disable keyboard command (sets bit <4> of the 8042 command byte).
AEh Enable keyboard command (clears bit <4> of the 8042 command byte).
C0h Read input port of the 8042. This command directs the 8042 to transfer the contents of the input port to
the output buffer so that they can be read at port 60h. The contents are as follows:
Bit <7> Password Enable:
0 = Disabled, 1 = Enabled
Bit <6> External Boot Enable:
0 = Enabled, 1 = Disabled
Bit <5> Setup Enable:
0 = Enabled, 1 = Disabled
Bit <4> VGA Enable:
0 = Enabled, 1 = Disabled
Bit <3> Diskette Writes:
0 = Disabled, 1 = Enabled
Bit <2> Reserved
Bit <1> Pointing Device Data Input Line
Bit <0> Keyboard Data Input Line
C2h Poll Input Port High. This command directs the 8042 to place bits <7..4> of the input port into the upper
half of the status byte on a continous basis until another command is received.
C3h Poll Input Port Low. This command directs the 8042 to place bits <3..0> of the input port into the lower
half of the status byte on a continous basis until another command is received.
D0h Read output port. This command directs the 8042 to transfer the contents of the output port to the
output buffer so that they can be read at port 60h. The contents are as follows:
Bit <7> Keyboard data stream
Bit <6> Keyboard clock
Bit <5> IRQ12 (pointing device interrupt)
Bit <4> IRQ1 (keyboard interrupt)
Bit <3> Pointing device clock
Bit <2> Pointing device data
Bit <1> A20 Control:
0 = Hold A20 low
1 = Enable A20
Bit <0> Reset Line Status;
0 = Inactive
1 = Active
D1h W rite output port. This command directs the 8042 to place the next byte written to port 60h into the
output port (only bit <1> can be changed).
D2h Echo keyboard data. Directs the 8042 to send back to the CPU the next byte written to port 60h as if it
originated from the keyboard. No 11-to-9 bit translation takes place but an interrupt (IRQ1) is generated
if enabled.
D3h Echo pointing device data. Directs the 8042 to send back to the CPU the next byte written to port 60h
as if it originated from the pointing device. An interrupt (IRQ12) is generated if enabled.
D4h W rite to pointing device. Directs the 8042 to send the next byte written to 60h to the pointing device.
E0h Read test inputs. Directs the 8042 to transfer the test bits 1 and 0 into bits <1,0> of the output buffer.
F0h-FFh Pulse output port. Controls the pulsing of bits <3..0> of the output port (0 = pulse, 1 = don't pulse).
Note that pulsing bit <0> will reset the system.
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5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR
The legacy model provides separate PS/2 connectors for the keyboard and pointing device. Both
connectors are identical both physically and electrically. Figure 5-7 and Table 5-14 show the
connector and pinout of the keyboard/pointing device interface connectors.
6 5
4 3
2 1
Figure 5-7. Keyboard or Pointing Device Interface Connector
(as viewed from rear of chassis)
Table 514. Keyboard/Pointing Device Connector Pinout
Table 5-17.
Keyboard/Pointing Device Connector Pinout
Pin Signal Description Pin Signal Description
1 DATA Data 4 + 5 VDC Power
2 NC Not Connected 5 CLK Clock
3 GND Ground 6 NC Not Connected
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Chapter 5 Input/Output Interfaces
5.7 UNIVERSAL SERIAL BUS INTERFACE
The Universal Serial Bus (USB) interface provides USB 1.1-compliant asynchronous/isochronous
data transfers of up to 12 Mb/s. This high-speed interface supports hot-plugging of compatible
devices, making possible system configuration changes without powering down or even rebooting
systems. The USB uses a tiered scheme for connecting multiple devices. A USB device may be
connected directly to the computer's USB port or daisy-chained off another USB device connected
to the computer. Up to 127 USB devices may be connected (tiered) to the host (computer).
NOTE: It is recommended to run the Windows 98 (or later) operating system when using
USB peripherals, especially a USB keyboard and USB mouse. Problems may be
encountered when using USB devices with a system running Windows 95, although some
peripherals may operate satisfactorily.
As shown in Figure 5-8, USB interfacing is provided by the 82801 ICH or ICH2 component and a
TPS2054 or TUS2046B hub component.
Rear Panel J111
USB Data 2
USB Port 0
USB Data 0
Rear Panel USB Port 1
82801
USB Port 0
ICH2
Rear Panel J112
USB Port 1
82801 USB
USB Port 2
ICH USB
USB USB
Data 0
USB Port 2 Cntlr. A
Hub Data 1
USB Port 3
USB
USB
Data 1
Cntlr. Front Panel
USB Front Panel J110
USB
USB Port 3 USB Hub
Cntlr. B USB Port 4
Data 3
NC
USB Port 4
USB Port 5
USB Port 6
IPAQ 1.0/1.2 System IPAQ 2.0 System
Legacy-free systems only Not connected Direct port
Figure 5-8. USB I/F, Block Diagram
Legacy-free iPAQ 1.0/1.2 and all iPAQ 2.0 systems provide both direct-controller and through-hub
USB connections for USB peripherals. For maximum efficiency, direct-controller ports should be
reserved for connection with a high-data throughput device such as a digital camera or CD. On
iPAQ 2.0 systems, USB port 0 (upper left as viewed from rear) is a dedicated-direct port that
assures full speed operation with a USB device. Through-hub ports can efficiently handle multiple
(daisy-chained) devices such as a keyboard and mouse that require only intermittent or low
capacity data.
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5.7.1 USB DATA FORMATS
The USB I/F uses non-return-to-zero inverted (NRZI) encoding for data transmissions, in which a
1 is represented by no change (between bit times) in signal level and a 0 is represented by a change
in signal level. Bit stuffing is employed prior to NRZ1 encoding so that in the event a string of 1's
is transmitted (normally resulting in a steady signal level) a 0 is inserted after every six consecutive
1's to ensure adequate signal transitions in the data stream.
The USB transmissions consist of packets using one of four types of formats (Figure 5-9) that
include two or more of seven field types.
Sync Field 8-bit field that starts every packet and is used by the receiver to align the
incoming signal with the local clock.
Packet Identifier (PID) Field 8-bit field sent with every packet to identify the attributes (in.
out, start-of-frame (SOF), setup, data, acknowledge, stall, preamble) and the degree of error
correction to be applied.
Address and Endpint Fields 7- and 4-bit fields (respectively) that provide source/destination
information required in token packets.
Frame Field 11-bit field sent in Start-of-Frame (SOF) packets that are incremented by the
host and sent only at the start of each frame.
Data Field 0-1023-byte field of data.
Cyclic Redundancy Check (CRC) Field 5- or 16-bit field used to check transmission
integrity.
Sync Field PID Field Addr. ENDP. CRC Field
Token Packet (8 bits) (8 bits) Field Field (5 bits)
(7 bit ) (4 bit )
Sync Field PID Field Frame Field CRC Field
SOF Packet (8 bits) (8 bits) (11 bits) (5 bits)
Sync Field PID Field Data Field CRC Field
Data Packet (8 bits) (8 bits) (0-1023 bytes) (16 bits)
Sync Field PID Field
Handshake Packet
(8 bits) (8 bits)
Figure 5-9. USB Packet Formats
Data is transferred LSb first. A cyclic redundancy check (CRC) is applied to all packets (except a
handshake packet). A packet causing a CRC error is generally completely ignored by the receiver.
Compaq iPAQ Series of Desktop Personal Computers 5-23
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Chapter 5 Input/Output Interfaces
5.7.2 USB PROGRAMMING
Programming the USB interface consists of configuration, which typically occurs during POST,
and control, which occurs at runtime. The USB interface may be inhibited (through Setup) on
legacy systems for security purposes.
5.7.2.1 USB Configuration
The USB interface functions as a PCI device (31) within the 82801 component (function 2) and is
configured using PCI Configuration Registers as listed in Table 5-15.
Table 515. USB Interface Configuration Registers
Table 5-15.
USB Interface Configuration Registers
PCI
PCI
Config. Reset
Config. Reset
Addr. Register Value
Addr. Register Value
00, 01h Vender ID 8086h 0Dh Latency Timer 00h
| 161685-B21
7M-0300B-WW
|
