02, 03h Device ID [1] 0Eh Header Type 00h
04, 05h PCI Command 0000h 20-23h I/O Space Base Address 1h
06, 07h PCI Status 0280h 3Ch Interrupt Line 00h
08h Revision ID 00h 3Dh Interrupt Pin 04h
09h Programming I/F 00h 60h Miscellaneous Control 1 10h
0Ah Sub Class Code 03h C0, C1h Miscellaneous Control 2 2000h
0Bh Base Class Code 0Ch C4h USB Resume Enable 00h
NOTE:
[1] 2412h = USB controller A, 2444h = USB controller B
5.7.2.2 USB Control
The USB is controlled through I/O registers as listed in table 5-16.
Table 516. USB Control Registers
Table 5-16.
USB Control Registers
I/O Addr. Register Default Value
00, 01h Command 0000h
02, 03h Status 0000h
04, 05h Interupt Enable 0000h
06, 07 Frame Number 0000h
08, 0B Frame List Base Address 0000h
0Ch Start of Frame Modify 40h
10, 11h Port 1 Status/Control 0080h
12, 13h Port 2 Status/Control 0080h
18h Test Data 00h
5-24 Compaq iPAQ Series of Desktop Personal Computers
Second Edition February 2001
Technical Reference Guide
5.7.3 USB CONNECTOR
The USB ports use series-A connectors.
1 2 3 4
Figure 5-10. Universal Serial Bus Connector
Table 517. USB Connector Pinout
Table 5-17.
USB Connector Pinout
Pin Signal Description Pin Signal Description
1 Vcc +5 VDC 3 USB+ Data (plus)
2 USB- Data (minus) 4 GND Ground
5.7.4 USB CABLE DATA
The recommended cable length between the host and the USB device should be no longer than
sixteen feet for full-channel (12 MB/s) operation, depending on cable specification (see following
table).
Table 518. USB Cable Length Data
Table 5-18.
USB Cable Length Data
Conductor Size Resistance Maximum Length
0.036
20 AWG 16.4 ft (5.00 m)
0.057
22 AWG 9.94 ft (3.03 m)
0.091
24 AWG 6.82 ft (2.08 m)
0.145
26 AWG 4.30 ft (1.31 m)
0.232
28 AWG 2.66 ft (0.81 m)
NOTE:
For sub-channel (1.5 MB/s) operation and/or when using sub-standard cable
shorter lengths may be allowable and/or necessary.
The shield, chassis ground, and power ground should be tied together at the host end but left
unconnected at the device end to avoid ground loops.
Color code:
Signal Insulation color
Data + Green
Data - W hite
Vcc Red
Ground Black
Compaq iPAQ Series of Desktop Personal Computers 5-25
Second Edition - February 2001
Chapter 5 Input/Output Interfaces
5 .8 AUDIO SUBSYSTEM
A PCI audio subsystem is integrated onto the system board of the Compaq iPAQ. Implementing
AC'97 design guidelines, the audio subsystem is designed to provide optimum sound. Key features
of the audio subsystem include:
AC'97 ver. 2.1 compliance
Multiple audio channel streaming
Soft CD, DVD/AC-3 processing
Wavetable synthesis utilizing system memory
Acoustic echo cancellation
16-bit stereo PCM input and output w/ up to 48 KHz sampling
5.8.1 FUNCTIONAL ANALYSIS
A block diagram of the audio subsystem is shown in Figure 5-11. The architecture uses the AC'97
Audio Controller of the 82801 component to access and control an Analog Devices AD188x
Audio Codec, which provides the analog-to-digital (ADC) and digital-to-analog (DAC)
conversions as well as the mixing functions.
All control functions such as volume, audio source selection, and sampling rate are controlled
through software over the PCI bus through the AC97 Audio Controller of the 82801 ICH. Control
data and digital audio streams (record and playback) are transferred between the Audio Controller
and the Audio Codec over the AC97 Link Bus. Playback audio from the Audio Codec is routed to
a low-distortion mono amplifier that drives a long-excursion large-magnet speaker for optimum
sound.
The analog interfaces allowing connection to external audio devices are discussed in the following
paragraphs.
Mic In - This front panel-accessible input uses a three-conductor (stereo) mini-jack that is
specifically designed for connection of a condenser microphone with an impedance of 10-K ohms.
This is the default recording input after a system reset.
Line In - This input uses a three-conductor (stereo) mini-jack that is specifically designed for
connection of a high-impedance (10k-ohm) audio source such as a tape deck or audio CD player.
Headphones Out - This front panel-accessible input uses a three-conductor (stereo) mini-jack that
is specifically designed for connecting a set of 16-ohm (nom.) stereo headphones. Plugging into
the Headphones jack mutes the signal to the internal speaker and the Line Out jack.
Line Out - This output uses a three-conductor (stereo) mini-jack for connecting left and right
channel line-level signals (20-K ohm impedance). A typical connection would be to a tape
recorder's Line In (Record In) jacks, an amplifier's Line In jacks, or to "powered" speakers that
contain amplifiers. Plugging into the Line Out mutes the internal speaker.
5-26 Compaq iPAQ Series of Desktop Personal Computers
Second Edition February 2001
Technical Reference Guide
+
PC Beep Audio TDA Internal
82801AA ICH
-
7056 Speaker
PCI Bus AC97
AC'97 Link Bus
Audio
Cntlr.
Audio (L)
Line
Bias (R)
Mic In
Out
AD1881 PB Audio
(L)
Audio (L/R)
Line In (L)
(R) Headphones
Codec
(R) Out
CD Audio (L)
CD ROM
CD Audio (L)
In Multibay
iPAQ 1.x System
iPAQ 2.0 System
82801BA ICH2 PC Beep Audio
PCI Bus AC97
AC'97 Link Bus
Audio
Cntlr.
+
Audio Internal
Mono Audio Out TDA
- Speaker
Bias 1517
Mic In
Line Plug Sense
Line Audio (L/R) (L)
AD1885
(L) Line
(R)
Audio
Line In (R) Out
Codec
HP Audio (L/R) (L) Headphones
(R)
CD Audio (L) Out
CD ROM
CD Audio (L)
In Multibay
HP Plug Sense
Figure 5-11. Audio Subsystem Functional Block Diagram
The functionality of the iPAQ 1.x and iPAQ 2.0 audio systems is basically the same. The method
of muting the internal speaker with insertion of a Line In or Headphone plug differs between the
two codec types (mechanical (AD1881) versus logic (AD1885)) and the iPAQ 2.0 features an 8-
watt speaker amplifier versus the 5-watt amplifier of the iPAQ 1.x.
Compaq iPAQ Series of Desktop Personal Computers 5-27
Second Edition - February 2001
Chapter 5 Input/Output Interfaces
5.8.2 AC97 AUDIO CONTROLLER
The AC97 Audio Controller is a PCI device (device 31/function 5) that is integrated into the 82801
ICH component and supports the following functions:
Read/write access to audio codec registers
16-bit stereo PCM input and output @ up to 48 KHz sampling
Acoustic echo correction for microphone
AC'97 Link Bus
ACPI power management
5.8.3 AC97 LINK BUS
The audio controller and the audio codec communicate over a five-signal AC97 Link Bus (Figure
5-12). The AC97 Link Bus includes two serial data lines (SD OUT/SD IN) that transfer control
and PCM audio data serially to and from the audio codec using a time-division multiplexed (TDM)
protocol. The data lines are qualified by a 12.288 MHz BIT_CLK signal driven by the audio
codec. Data is transferred in frames synchronized by the 48-KHz SYNC signal, which is derived
from the clock signal and driven by the audio controller. The SYNC signal is high during the
frame's tag phase then falls during T17and remains low during the data phase. A frame consists of
one 16-bit tag slot followed by twelve 20-bit data slots. When asserted (typically during a power
cycle), the RESET- signal (not shown) will reset all audio registers to their default values.
T1 T2 T38 T39 T58
T18 T19
3
BIT_CLK
(12.288 MHz)
SYNC
(48 KHz)
Codec Bit 15 Bit 14
SD OUT Bit 0 Bit 19 Bit 18 Bit 0 Bit 19 Bit 18 Bit 0 Bit 19
Ready
or SD IN
Slot 0 Slot 1 Slot 2
(Tag) (Data) (Data)
Slot Description
0 Bit 15, Frame valid bit; Bits 14-3, Slots 1-12; valid bits; Bits 2-0, Codec ID
1 Command address: Bit 19, R/W; Bits 18..12, reg. Index; Bits 11..0, reserved.
2 Command data
3 Bits 19-4: PCM audio data, left channel (SD OUT, playback; SD IN, record)
Bits 3-0 all zeros
4 Bits 19-4: PCM audio data, right channel (SD OUT, playback; SD IN, record)
Bits 3-0 all zeros
5 Modem codec data (not used in this system)
6-11 Reserved
12 I/O control
Figure 5-12. AC'97 Link Bus Protocol
5-28 Compaq iPAQ Series of Desktop Personal Computers
Second Edition February 2001
Technical Reference Guide
5.8.4 AUDIO CODEC
The audio codec provides pulse code modulation (PCM) coding and decoding of audio
information as well as the selection and/or mixing of analog channels. As shown in Figure 5-13,
analog audio from a microphone, tape, or CD can be selected and, if to be recorded (saved) onto a
disk drive, routed through an analog-to-digital converter (ADC). The resulting left and right PCM
record data are muxed into a time-division-multiplexed (TDM) data stream (SD IN signal) that is
routed to the audio controller. Playback (PB) audio takes the reverse path from the audio controller
to the audio codec as SD OUT data and is decoded and processed by the digital-to-analog
converter (DAC). The codec supports simultaneous record and playback of stereo (left and right)
audio. The Sample Rate Generator may be set for sampling frequencies up to 48 KHz.
Analog audio may then be routed through 3D stereo enhancement processor or bypassed to the
output selector (SEL). The integrated analog mixer provides the computer control-console
functionality handling multiple audio inputs.
Audio
Format
Mic In S
Rec
Left
e
Data (L)
Audio
Line In (L) Rec
l ADC
Gain
e
Line In (R) SD IN
Rec
c Right
Data (R)
t Audio Rec
CD In (L) ADC
o Gain
CD In (R) r
AC97 Audio
Sample
Link Controller
Rate
I/F
/Mixer Via Link Bus
Gen.
SW PB
(L)
3D Proc. Data (L)
PB
(L)
DAC
(L)
S Gain SD Out
Output E PB
(R)
(R)
Am p L 3D Proc. Data (R)
PB
(R) DAC
Gain
Figure 5-13. AD1881 or AD1885 Audio Codec Functional Block Diagram
All inputs and outputs are two-channel stereo except for the microphone input, which is inputted as
a single-channel but mixed internally onto both left and right channels. The microphone input is
the default active input. All block functions are controlled through index-addressed registers of the
codec.
Compaq iPAQ Series of Desktop Personal Computers 5-29
Second Edition - February 2001
Chapter 5 Input/Output Interfaces
5.8.5 AUDIO PROGRAMMING
Audio subsystem programming consists configuration, typically accomplished during POST, and
control, which occurs during runtime. The register maps are described in the following
subsections.
5.8.5.1 Audio Configuration
The audio subsystem is configured according to PCI protocol through the AC'97 audio controller
function of the 82801 ICH. Table 5-19 lists the PCI configuration registers of the audio subsystem.
Table 519. AC'97 Audio Controller PCI Configuration Registers
Table 5-19.
AC'97 Audio Controller
PCI Configuration Registers (82801 Device 31/Function 5)
PCI Reset PCI Reset
Addr. Register Value Addr. Register Value
00-01h Vender ID 8086h 14-17h Native Audio Bus Mstr. Addr. 1h
02-03h Device ID [1] 18-1Bh Reserved 1h
04-05h PCI Command 0000h 1C-2Bh Reserved 1h
06-07h PCI Status 0280h 2C-2Dh Subsystem Vender ID 0000h
08h Revision ID xxh 2E-2Fh Subsystem ID 0000h
09h Programming 01h 30-3Bh Reserved 0's
0Ah Sub-Class 01h 3Ch Interrupt Line 00h
0Bh Base Class Code 04h 3Dh Interrupt Pin 03h
0Eh Header Type 00h 3E-FFh Reserved 0's
10-13h Nat. Audio Mixer Base Addr. 1h -- -- --
NOTE:
[1] 2415h = 82801AA ICH, 2445h = 82801BA ICH2.
5.8.5.2 Audio Control
The audio subsystem is controlled through a set of indexed registers that physically reside in the
audio codec . The register addresses are decoded by the audio controller and forwarded to the
audio codec over the AC97 Link Bus previously described. The audio codec's control registers
(Table 5-20) are mapped into 64 kilobytes of variable I/O space.
Table 520. AC'97 Audio Codec Control Registers
Table 5-20.
AC'97 Audio Codec Control Registers
Value
Value
Value
On
On Offset
On Offset
Offset
Reset
Reset Addr. / Register
Reset Addr. / Register
Addr. / Register
00h Reset 0100h 14h Video Vol. 8808h 28h Ext. Audio ID. 0001h
02h Master Vol. 8000h 16h Aux Vol. 8808h 2Ah Ext. Audio Ctrl/Sts 0000h
04h Reserved X 18h PCM Out Vol. 8808h 2Ch PCM DAC SRate BB80h
06h Mono Mstr. Vol. 8000h 1Ah Record Sel. 0000h 32h PCM ADC SRate BB80h
08h Reserved X 1Ch Record Gain 8000h 34h Reserved X
0Ah PC Beep Vol. 8000h 1Eh Reserved X 72h Reserved X
0Ch Phone In Vol. 8008h 20h Gen. Purpose 0000h 74h Serial Config. 7x0xh
0Eh Mic Vol. 8008h 22h 3D Control 0000h 76h Misc. Control Bits 0404h
10h Line In Vol. 8808h 24h Reserved X 7Ch Vender ID1 4144h
12h CD Vol. 8808h 26h Pwr Mgnt. 000xh 7Eh Vender ID2 5340h
5-30 Compaq iPAQ Series of Desktop Personal Computers
Second Edition February 2001
Technical Reference Guide
5.8.6 AUDIO SPECIFICATIONS
The specifications of the audio subsystem are listed in Table 5-21.
Table 521. Audio Subsystem Specifications
Table 5-21.
Audio Subsystem Specifications
Paramemter Measurement
Sampling Rate 7.04 KHz to 48 KHz
Resolution 16-bit (1 Hz)
Nominal Input Voltage:
Mic In (w/+20 db gain .283 Vp-p
Line In 2.83 Vp-p
Impedance:
Mic In 1 K ohms (nom)
Line In 10 K ohms (min)
Line Out 800 ohms
Signal-to-Noise Ratio (Line in to Line Out) 90 dB (min)
Max. Power To Speaker (8 ohms):
iPAQ 1.x 5.2 watts
iPAQ 2.0 8.0 watts
Total Harmonic Distortion (THD) to speaker:
@ 0.5 watts 1%
@ max. power output 10 %
Headphone Output Power (into 32 ohms) 60 mW
Input Gain Attenuation Range 46.5 dB
Master Volume Range -94.5 dB
Frequency Response:
Codec 20-20 KHz
Speaker 450 - 4000 Hz
Compaq iPAQ Series of Desktop Personal Computers 5-31
Second Edition - February 2001
Chapter 5 Input/Output Interfaces
5 .9 NETWORK INTERFACE CONTROLLER
All Compaq iPAQ systems include a network interface controller (NIC) on the system board
supported by an RJ-45 connector with two LED indicators. The iPAQ 1.x system uses an 82559
Ethernet Controller component while the iPAQ 2.0 system uses equivalent logic integrated into the
ICH2 component. The following discussion applies to both systems, which are functionally the
same.
The NIC supports speeds of 10 and 100 Mbs in half- or full-duplex modes, and provides IEEE
802.3u auto-negotiation. Half-duplex operation features an Intel-proprietary collision reduction
mechanism while full-duplex operation follows the IEEE 802.3x flow control specification.
Transmit and receive FIFOs of 3 kilobytes each reduce the chance of overrun while waiting for bus
access.
25 MHz
Clock
EEP/
Circuitry RJ-45
ROM
Connector
CLK Active/
PCI Bus Link
(Green)
825xx
TX/RX PHY TX/RX
Ethernet
82801 ICH I/F
Controller
SMBus
Speed
(Yellow)
LED Function
Green Activity/Link: Indicates network activity and link pulse
reception.
Yellow Speed: Indicates link detection in 100 MB/s mode
(always on if 100Base-Tx is forced).
Figure 5-14. Network Interface Controller Block Diagram
The Intel 825xx Ethernet Controller includes the following features:
Intel 82559 Fast Ethernet controller with 32-bit architecture and 3-KB TX/RX buffers.
Dual-mode support with auto-switching between 10BASE-T and 100BASE-TX.
Power down and Wake up support in both APM and ACPI environments (PME- and WOL).
Alert-on-LAN (AOL v1.0) support.
Dual control (PCI and SM bus interfaces).
Link and Activity LED indicator drivers
The 825xx controller features high and low priority queues and provides priority-packet (Quality
of Service or "QOS") processing for networks that can support that feature. The controller's micro-
machine processes transmit and receive frames independently and concurrently. Receive runt
(under-sized) frames are not passed on as faulty data but discarded by the controller, which also
directly handles such errors as collision detection or data under-run. Identification, configuration
and connection parameters are held in an EEPROM.
5-32 Compaq iPAQ Series of Desktop Personal Computers
Second Edition February 2001
Technical Reference Guide
The NIC uses 3.3 VDC auxiliary power, which allows the 825xx controller to support Wake-On-
LAN (WOL) and Alert-On-LAN (AOL) functions while the main system is powered down.
NOTE: For the WOL and AOL features to function as described in the following
paragraphs, the system unit must be plugged into a live AC outlet to allow the power
supply to produce the 3.3 VDC auxiliary voltage. Controlling unit power through a
switchable power strip will, with the strip turned off, disable WOL and AOL
functionality.
5.9.1 WAKE ON LAN
The NIC supports the Wired-for-Management (WfM) standard of Wake-On-LAN (WOL) that
allows the system to be booted up from a powered down condition upon the detection of special
packets received over a network. Magic Packet wakeup is supported in S5 (off), S4, S3, and S1
states. Pattern Match wakeup is supported in S4, S3, and S1 states. A detected packet will result in
the NIC asserting the PCI bus signal PME-, which is used by the chipset to initiate the wakeup
sequence.
5.9.2 ALERT ON LAN
Alert-On-LAN (AOL) support allows the NIC to communicate the occurrence of certain events
over a network even while the system unit is powered off. In a system-off (powered down)
condition the 82801 ICH and the 825xx NIC components receive auxiliary +3.3 VDC power
(derived from the +5 VDC auxiliary power from the power supply assembly). Certain events
(listed in Table 5-22) detected by the 82801 ICH will result in the ICH generating an alert message
over the SMBus to the NIC. Upon receiving the alert message from the ICH the NIC transmits the
appropriate pre-constructed message over the network to a system management console.
Reportable AOL events are listed in the following table:
Table 522. AOL Events
Table 5-22.
AOL Events
Event Description
BIOS Failure System fails to boot successfully.
OS Problem System fails to load operating system after POST.
Missing/Faulty Processor Processor fails to fetch first instruction.
Thermal Condition Thermal ASIC reports high temperature.
Heartbeat Indication of system's network presence (sent approximately every 30
seconds in normal operation).
The AOL implementation requirements are as follows:
1. Intel PRO/100+ Management Adapter driver (v3.1x for iPAQ 1.x, v3.8 for iPAQ 2.0) or later
(available from Compaq).
2. Client-side utility agent software and utilities (available from Compaq).
3. Management console running one of the following:
a. HP OpenView Network Node Manager 6.x
b. Intel LANDesk Client Manager
c. Compaq Insight Manager
Compaq iPAQ Series of Desktop Personal Computers 5-33
Second Edition - February 2001
Chapter 5 Input/Output Interfaces
5.9.3 POWER MANAGEMENT SUPPORT
The 825xx controller features Wired-for-Management (WfM) support providing system wake up
from network events (WOL) as well as generating system status messages (AOL) and supports
both APM and ACPI power management environments. The controller receives 3.3 VDC
(auxiliary) power as long as the system is plugged into a live AC receptacle, allowing support of
wake-up events occuring over a network while the system is powered down or in a low-power
state.
5.9.3.1 APM Environment
The Advanced Power Management (APM) functionality of system wake up is implemented
through the system's APM-compliant BIOS and the controller's Magic Packet-compliant
hardware. This environment bypasses operating system (OS) intervention allowing a plugged in
unit to be turned on remotely over the network (i.e., "remote wake up"). In APM mode the
controller, will respond upon receiving a Magic Packet, which is a packet where the node's address
is repeated 16 times. Upon Magic packet detection, the controller intitiates the boot sequence.
5.9.3.2 ACPI Environment
The Advanced Configuration and Power Interface (ACPI) functionality of system wake up is
implemented through an ACPI-compliant OS and is the default power management mode. The
following wakeup events may be individually enabled/disabled through the supplied software
driver:
Magic Packet Packet with node address repeated 16 times in data portion
NOTE: The following functions are supported in NDIS5 drivers but implemented
through remote management software applications (such as LanDesk).
Individual address match Packet with matching user-defined byte mask
Multicast address match Packet with matching user-defined sample frame
ARP (address resolution protocol) packet
Flexible packet filtering Packets that match defined CRC signature
5-34 Compaq iPAQ Series of Desktop Personal Computers
Second Edition February 2001
Technical Reference Guide
5.9.4 NIC PROGRAMMING
Programming the NIC controller consists of configuration, which occurs during POST, and
control, which occurs at runtime.
5.9.4.1 Configuration
The 825xx controller is a PCI device and configured though PCI configuration space registers
using PCI protocol described in chapter 4. The PCI configuration registers are listed in the
following table:
Table 523. NIC Controller PCI Configuration Registers
Table 5-23.
NIC Controller PCI Configuration Registers
PCI Reset PCI Reset
Addr. Register Value Addr. Register Value
00-01h Vender ID 8086h 10-13h Cntrl. Reg. Base Addr. (Mem) 0000h
02-03h Device ID [1] 14-17h Cntrl. Reg. Base Addr. (I/O) 00h
04-05h PCI Command 0000h 18-1Bh Flash Mem. Base Addr. 00h
06-07h PCI Status 0280h 2C-2Dh Subsystem Vender ID
08h Revision ID xxh 2E-2Fh Subsystem ID
09-0Bh Class Code 01h 30-33h Expansion ROM Base Addr.
0Ch Cache Line Size 01h 34h Capabilities Pointer DCh
0Dh Latency Timer 04h 3C-3D Interrupt Line/Pin
0Eh Header Type 00h 3E-3Fh Min Gnt/Max Lat
0Fh BIST 00h DC-E3h Power Mgmt. Functions
NOTE:
Assume unmarked gaps are reserved and/or not used.
[1] iPAQ 1.x = 1229h (Function 0, Device #2); iPAQ 2.0 = 2449h (Function 0, Device # 8).
5.9.4.2 Control
The 82559 controller is controlled though registers that may be mapped in system memory space
or variable I/O space. The registers are listed in the following table:
Table 524. NIC Control Registers
Table 5-24.
NIC Control Registers
Offset No. of Offset No. of
Addr. / Register Bytes Addr. / Register Bytes
00h SCB Status 2 19h Flow Control Register 2
02h SCB Command 2 1Bh PMDR 1
04h SCB General Pointer 4 1Ch General Control 1
08h PORT 4 1Dh General Status 1
0Ch Flash Control Reg. 2 1E-2Fh Reserved 10
0Eh EEPROM Control Reg. 2 30h Function Event Register 4
10h Mgmt. Data I/F Cntrl. Reg. 4 34h Function Event Mask Register 4
14h Rx Direct Mem. Access Byte Cnt. 4 38h Function Present State Register 4
18h Early Receive Interrupt 1 20h Force Event Register 4
Not implemented in these systems (CardBus registers).
Compaq iPAQ Series of Desktop Personal Computers 5-35
Second Edition - February 2001
Chapter 5 Input/Output Interfaces
5.9.4.3 RJ-45 Connector
Figure 5-15 shows the RJ-45 connector used for the NIC interface. This connector includes the two
status LEDs as part of the connector assembly.
Activity LED
Speed LED
P in Description
1 Transmit+
2 Transmit-
3 Receive+
6 Receive-
87654321
Figure 5-15. Ethernet TPE Connector (RJ-45, viewed from card edge)
5.9.4.4 825xx NIC Specifications
Table 525. 825xx NIC Operating Specifications
Table 5-25.
825xx NIC Specifications
Parameter
Modes Supported 10BASE-T half duplex @ 10 MB/s
10Base-T full duplex @ 20 MB/s
100BASE-TX half duplex @ 100 MB/s
100Base-TX full duplex @ 200 MB/s
Standards Compliance IEEE VLAN (802.1A)
IEEE 802.2
IEEE 802.3 & 802.3u
IEEE Intel priority packet (801.1p)
OS Driver Support MS Windows 95,98, 2000, Me
MS Windows NT 3.51 & 4.0
Novell Netware 3.11, 3.12, & 4.1x; 5 Server
Sunsoft Solaris
SCO UnixWare
Open Desktop
OpenServer
Boot ROM Support Intel PRO/100 Boot Agent (PXE 2.0, RPL)
F12 BIOS Support Yes
Bus Inteface PCI 2.2
Power Management Support APM, ACPI, PCI Power Management Spec.
5-36 Compaq iPAQ Series of Desktop Personal Computers
Second Edition February 2001
Technical Reference Guide
Chapter 6
GRAPHICS SUBSYSTEM
6. Chapter 6 Graphics Subsystem
6 .1 INTRODUCTION
All Compaq iPAQ systems feature a graphics controller that is integrated into the chipset's
GMCH component. This "Direct AGP" graphics solution provides efficient, economical 2D/3D
performance.
This chapter covers the following subjects:
Functional description (6.2) page 6-2
Programming (6.3) page 6-5
Monitor power management (6.4) page 6-5
Monitor connector (6.5) page 6-6
Upgrading graphics (6.6) page 6-6
6.1.1 FEATURE SUMMARY
The graphics subsystem includes the following features:
Accelerated driver support for Windows 3.1/95/98/2000, Windows NT 4.0, OS/2
MS ActiveMovie and Media Player support for Win95
Direct 3D support
MS Direct Draw 5/6 support
DDC2B compliant
Accelerator engine support for:
3-ROP BitBLT
Line Draw
Color expansion
Video color conversion/scaling
Motion video
Triangle setup
4-MB Display Cache standard on Pentium III-based systems
Compaq iPAQ Series of Desktop Personal Computers 6-1
Second Edition - February 2001
Chapter 6 Graphics Subsystem
6 .2 FUNCTIONAL DESCRIPTION
The Intel 810E and 815E chipsets integrate the graphics controller into their GMCH component
(Figure 6-1). The graphics controller includes 2D and 3D accelerator engines working with a
deeply pipelined pre-processor. The controller supports perspective-correct texture mapping,
bilinear and anisotropic Mip-mapping, Alpha blending, Gouraud shading, and fogging.
82810E or 82815 GMCH
FSB
I/F
4 MB
AGP Bus
Display Cache [1]
3D/2D
SDRAM
Graphics
Controller
RGB Controller
Monitor
Hub
Link
Described in Chapter 3
Described in Chapter 4
[1] Standard on all Pentium III-based systems.
Optional for Celeron-based iPAQ 2.0 systems.
Figure 6-1. Graphics Subsystem, Block diagram
The graphics controller uses a portion of system memory for instructions, textures, and frame
(display) buffering. Using a process called Dynamic Video Memory Technology (DVMT), the
controller dynamically allocates display and texture memory amounts according to the needs of the
application. Pentium III-based systems also include four megabytes of Display Cache that can be
used for Z-buffering.
6-2 Compaq iPAQ Series of Desktop Personal Computers
Second Edition - February 2001
Technical Reference Guide
82810E or 82815 GMCH
Graphics Controller
3D
Engine
2D FSB I/F &
Pipelined
Engine SDRAM
Preprocessor
Cntlr.
HSync
HSync
Monitor RAM
Connector DAC AGP
RGB
I/F
Display Cache
Figure 6-2. GMCH Integrated Graphics Subsystem
The integrated graphics controller includes special enhancements for 2D operations. Motion
compensation logic is included to improve performance during software decoding of MPEG2
video. Hardware cursor and overlay engines relieve software processing and provide independent
gamma correction, saturation, and brightness control. The 230-MHz RAMDAC can support a
variable-scan rate monitor up to a maximum resolution of 1600 x 1200 with 256 colors. Video
BIOS for the controller is held in the system BIOS ROM and copied into system memory at
runtime for maximum performance.
On Pentium III-based systems, four megabytes of display cache is included that enhances 2D and
3D performance up to 30%. The local display cache allows the graphics controller to
simultaneously render graphics to the Z-buffer (in the display cache) while processing textures in a
portion of system memory, increasing 3D performance substantially. The integrated graphics
controller uses a specific amount of system memory. This memory is allocated as follows:
Video BIOS 512 or 1024 kilobytes. An OS report of available system memory will be the total
amount installed LESS this amount.
Graphics Memory Prior to the PV 4.x driver being loaded, the graphics memory will be one
megabyte for supporting standard VGA modes. After driver load, memory allocation will be set by
the Dynamic Video Memory Technology (DVMT) for rendering, Z-buffering, and displaying
according to need and total system memory availability. The following table indicates the amount
of memory allocated depending on operating system and memory availability.
OS Type and Total Graphics Memory Total Graphics Memory
Sys. Mem. Amount w/o 4-MB Display Cache w/ 4-MB Display Cache
W indows 98 w/32 MB 6 MB 9 MB
W indows 98 w/64 MB 10 MB 12 MB
W indows 98 w/128 MB 10 MB 12 MB
W indows NT 4.0 w/64 MB 9 MB 12 MB
W indows NT 4.0 w/128 MB 9 MB 12 MB
W indows 2000 w/64 MB 9 MB 12 MB
W indows 2000 w/128 MB 10 MB 12 MB
Compaq iPAQ Series of Desktop Personal Computers 6-3
Second Edition - February 2001
Chapter 6 Graphics Subsystem
6.2.1 DISPLAY MODES
The Intel graphics controller supports the following 2D display modes:
Table 6-1. Graphics Display Modes
Table 6-1.
Graphics Display Modes
Resolution Bits per pixel Color Depth Refresh Rate
640 x 480 8 256 60, 70, 72, 75, 85
640 x 480 16 65K 60, 70, 72, 75, 85
640 x 480 24 16.7M 60, 70, 72, 75, 85
720 x 480 8 256 75, 85
720 x 480 16 65K 75, 85
720 x 480 24 16.7M 75, 85
720 x 576 8 256 60, 75, 85
720 x 576 16 65K 60, 75, 85
720 x 576 24 16.7M 60, 75, 85
800 x 600 8 256 60, 70, 72, 75, 85
800 x 600 16 65K 60, 70, 72, 75, 85
800 x 600 24 16.7M 60, 70, 72, 75, 85
1024 x 768 8 256 60, 70, 72, 75, 85
1024 x 768 16 65K 60, 70, 72, 75, 85
1024 x 768 24 16.7M 60, 70, 72, 75, 85
1152 x 864 8 256 60, 70, 72, 75, 85
1152 x 864 16 65K 60, 70, 72, 75, 85
1152 x 864 [1] 24 16.7M 60, 70, 72, 75, 85
1280 x 720 8 256 60, 75, 85
1280 x 720 16 65K 60, 75, 85
1280 x 720 [1] 24 16.7M 60, 75, 85
1280 x 960 8 256 60, 75, 85
1280 x 960 16 65K 60, 75, 85
1280 x 960 [1] 24 16.7M 60, 75, 85
1280 x 1024 8 256 60, 70, 72, 75, 85
1280 x 1024 16 65K 60, 70, 72, 75, 85
1280 x 1024 [1] 24 16.7M 60, 70, 75, 85
1600 x 900 8 256 60, 75, 85
1600 x 900 16 65K 60, 75, 85
1600 x 1200 8 256 75
NOTE:
[1] True color (24-bpp) mode support requires the 4-MB Display Cache.
6-4 Compaq iPAQ Series of Desktop Personal Computers
Second Edition - February 2001
Technical Reference Guide
6.3 PROGRAMMING
The graphics controller is configured as a PCI device using PCI configuration registers listed in
Table 6-2.
Table 6-2. Graphics Controller PCI Configuration Registers
Table 6-2.
Graphics Controller PCI Configuration Registers
(GMCH, Device 2)
PCI
PCI
Config. Reset
Config. Reset
Addr. Register Value
Addr. Register Value
00, 01h Vendor ID 8086h 2E, 2Fh Subsystem ID 0000h
02, 03h Device ID [1] 30-33h Vid. BIOS Base Addr. 0's
04, 05h Command 0004h 34h Capabilities Pointer DCh
06, 07h Status 02B0h 3Ch Interrupt Line 00h
08h Revision ID 02h 3Dh Interrupt Pin 01h
0A, 0Bh Class Code 0003h 3Eh Min. Grant 00h
0Eh Header Type 01h 3Fh Max. Latency 00h
0Fh BIST 00h DC, DDh Pwr. Mgmt. Capabilities 0001h
10-13h Memory Range Addr. 8 DE, DFh Pwr. Mgmt. Capabilites 0022h
14-17h Mem. Mapped Range Addr. 0's E0, E1h Pwr. Mgmt. Control 0000h
2C, 2Dh Subsys. Vendor ID 0000h E2-FFh Reserved --
NOTES:
Assume unmarked locations/gaps as reserved. Refer to Intel documentation for detailed
register descriptions.
[1] iPAQ 1.0/1.2 (82810E) = 2502h; iPAQ 2.0 (82815) = 1132h
The graphics controller is controlled through memory-mapped registers by the appropriate
software driver.
6 .4 MONITOR POWER MANAGEMENT CONTROL
The controller provides monitor power control for monitors that conform to the VESA display
power management signaling (DPMS) protocol. This protocol defines different power
consumption conditions and uses the HSYNC and VSYNC signals to select a monitor's power
condition. Table 6-3 lists the monitor power conditions.
Table 6-3. Monitor Power Management Conditions
Table 6-3.
Monitor Power Management Conditions
HSYNC VSYNC Power Mode Description
Active Active On Monitor is completely powered up. If activated, the inactivity
counter counts down during system inactivity and if allowed to
tiemout, generates an SMI to initiate the Suspend mode.
Active Inactive Suspend Monitor's high voltage section is turned off and CRT heater
(filament) voltage is reduced from 6.6 to 4.4 VDC. The Off mode
inactivity timer counts down from the preset value and if allowed
to timeout, another SMI is generated and serviced, resulting in
the monitor being placed into the Off mode. Wake up from
Suspend mode is typically a few seconds.
Inactive Inactive Off Monitor's high voltage section and heater circuitry is turned off.
W ake up from Off mode is a little longer than from Suspend.
Compaq iPAQ Series of Desktop Personal Computers 6-5
Second Edition - February 2001
Chapter 6 Graphics Subsystem
6 .5 MONITOR CONNECTOR
A DB-15 connector is provided on the rear chassis for connection to an analog monitor. The pinout
for this connector is shown in Figure 6-3 and Table 6-5.
5 4 3 2 1
10 7
9 8 6
11
15 13 12
14
Figure 6-3. VGA Monitor Connector, (Female DB-15, as viewed from rear).
Table 6-4. DB-15 Monitor Connector Pinout
Table 6-5.
DB-15 Monitor Connector Pinout
Pin Signal Description Pin Signal Description
1 R Red Analog 9 PW R +5 VDC (fused) [1]
2 G Blue Analog 10 GND Ground
3 B Green Analog 11 NC Not Connected
4 NC Not Connected 12 SDA DDC2-B Data
5 GND Ground 13 HSync Horizontal Sync
6 R GND Red Analog Ground 14 VSync Vertical Sync
7 G GND Blue Analog Ground 15 SCL DDC2-B Clock
8 B GND Green Analog Ground -- -- --
NOTES:
[1] Fuse automatically resets when excessive load is removed.
6.6 UPGRADING GRAPHICS
The graphics subsystem of the iPAQ 1.0/1.2 system is not upgradeable. The graphics subsystem of
iPAQ 2.0 systems that do not include the 4-MB display cache module (as is the case with Celeron-
based systems) may be upgraded by adding the 4-MB display cache module.
6-6 Compaq iPAQ Series of Desktop Personal Computers
Second Edition - February 2001
Technical Reference Guide
Chapter 7
POWER and SIGNAL
DISTRIBUTION
7. Chapter 7 POWER SUPPLY AND DISTRIBUTION
7 .1 INTRODUCTION
This chapter describes the power supply and method of general power and signal distribution.
Topics covered in this chapter include:
Power supply assembly/control (7.2) page 7-1
Power distribution (7.3) page 7-5
Signal distribution (7.4) page 7-7
7.2 POWER SUPPLY ASSEMBLY/CONTROL
This system features a power supply assembly that is controlled through programmable logic
(Figure 7-1).
System Board
Power On/Off
Logic &
Voltage Regulators
Power On
+3.3 +5
VDC AUX
Fan
PS
Off
On
110/220 VAC
AC Outlet
+5 VDC
+5 VDC
110 VAC -5 VDC Drives
Power Supply
110/220 VAC +12 VDC
+12 VDC
Assembly
Select SW
-12 VDC
220 VAC
Figure 71. Power Distribution and Control, Block Diagram
7-1
Compaq iPAQ Series of Desktop Personal Computers
Second Edition - February 2001
Chapter 7 Power and Signal Distribution
7.2.1 POWER SUPPLY ASSEMBLY
The power supply assembly is contained in a single unit that features a selectable input voltage:
90-132 VAC and 180-264 VAC. These systems use a 90-watt power supply. The specifications are
listed in Tables 7-1 and 7-2.
Table 7-1. iPAQ 90-Watt Power Supply Assembly Specifications
Table 7-1.
iPAQ 1.x 90-Watt Power Supply Assembly Specifications (P/N 159447)
Range/ Min. Current Max. Surge Max.
Tolerance Loading [1] Current Current [2] Ripple
Input Line Voltage:
110 VAC Setting 90 - 132 -- -- -- --
220 VAC Setting VAC -- -- -- --
180-264
VAC
Line Frequency 47 - 63 Hz -- -- -- --
Steady State Input (VAC) Current -- -- 3.0 A -- --
0.50 A 6.00 A 6.00 A 50 mV
+3.3 VDC Output + 5%
0.70 A 10.0 A 12.0 A 50 mV
+5 VDC Output +5%
0.00 A 2.50 A 2.50 A 50 mV
+5 AUX Output +4%
0.05 A 1.50 A 3.50 A 120 mV
+12 VDC Output +5%
0.00 A 0.30 A 0.30 A 200 mV
-12 VDC Output + 10 %
NOTES:
[1] Minimum loading requirements must be met at all times to ensure normal operation
and specification compliance.
[2] Surge duration no longer than 10 seconds and +12 tolerance +/- 10%.
Table 7-2. iPAQ 2.0 90-Watt Power Supply Assembly Specifications
Table 7-1.
iPAQ 2.0 90-Watt Power Supply Assembly Specifications (P/N 216922 or 218584 [3])
Range/ Min. Current Max. Surge Max.
Tolerance Loading [1] Current Current [2] Ripple
Input Line Voltage:
110 VAC Setting 90 - 132 -- -- -- --
220 VAC Setting VAC -- -- -- --
180-264
VAC
Line Frequency 47 - 63 Hz -- -- -- --
Steady State Input (VAC) Current -- -- 3.0 A -- --
0.10 A 6.00 A 6.00 A 50 mV
+3.3 VDC Output + 5%
1.30 A 14.0 A 15.0 A 50 mV
+5 VDC Output +5%
0.00 A 3.00 A 3.00 A 50 mV
+5 AUX Output +5%
0.05 A 1.50 A 3.00 A 120 mV
+12 VDC Output +5%
0.00 A 0.20 A 0.20 A 200 mV
-12 VDC Output + 10 %
NOTES:
[1] Minimum loading requirements must be met at all times to ensure normal operation
and specification compliance.
[2] Surge duration no longer than 10 seconds and +12 VDC tolerance + 10%.
[3] P/N 216922 is non-power factor correction (PFC) type. P/N 218584 is PFC type.
All power supply assemblies feature power line surge protection, withstanding brief surges of up to
2000 VAC without damage.
Compaq iPAQ Series of Desktop Personal Computers
7-2
Second Edition - February 2001
Technical Reference Guide
7.2.2 POWER CONTROL
The power supply assembly is controlled digitally by the PS On signal (Figure 7-1). When PS On
is asserted, the Power Supply Assembly is activated and all voltage outputs are produced. When
PS On is de-asserted, the Power Supply Assembly is off and no voltages (except +5 AUX) are
generated. Note that the +5 AUX voltage is always produced as long as the system is
connected to a live AC source.
The PS On signal can be controlled either by the Power Button or by the operating system (OS).
7.2.2.1 Power Button Control
The PS On signal is typically controlled through the Power Button which, when pressed and
released, applies a negative (grounding) pulse to the power control logic. The resultant action of
pressing the power button depends on the state and mode of the system at that time and is
described as follows:
System State Pressed Power Button Results In:
Off Negative pulse, of which the falling edge results in power control logic asserting PS
On signal to Power Supply Assembly, which then initializes. ACPI four-second
counter is not active.
On, ACPI Disabled Negative pulse, of which the falling edge causes power control logic to de-assert the
PS On signal. ACPI four-second counter is not active.
Full On, ACPI Enabled (Pressed and Released in Under Four Seconds):
Negative pulse, of which the falling edge causes power control logic to
generate SMI-, set a bit in the SMI source register, set a bit for button status,
and start four-second counter. Software should clear the button status bit
within four seconds and the Suspend state is entered. If the status bit is
not cleared by software in four seconds PS On is de-asserted and the
power supply assembly shuts down (this operation is meant as a guard if
the OS is hung).
(Pressed and Held At least Four Seconds Before Release):
PS On is negated, de-activating the power supply.
Suspend, ACPI Enabled (Pressed and Released in Under Four Seconds):
System wakes up to Full On.
(Pressed and Held At least Four Seconds Before Release):
System powers off.
7.2.2.2 OS Power Control
The PS On signal can be de-asserted by the ACPI-compliant operating system such as Windows
95. This system uses ACPI mode as the default power management mode, allowing the operating
system to shut off the system (once the user has selected that decision) without further user
intervention.
7-3
Compaq iPAQ Series of Desktop Personal Computers
Second Edition - February 2001
Chapter 7 Power and Signal Distribution
7 .3 POWER DISTRIBUTION
7.3.1 3.3/5/12 VDC DISTRIBUTION
The 3.3-, 5-, and 12-volt distribution is slightly different between the iPAQ 1.x system and the
iPAQ 2.0 system as described ion the following subsections.
7.3.1.1 iPAQ 1.0/1.2 POWER DISTRIBUTION
The iPAQ 1.0/1.2 power supply assembly includes a multi-connector cable assembly that routes
+3.3 VDC, +5 VDC, -5 VDC, +12 VC, and -12 VDC to the system board as well as to the
individual drive assemblies. Figure 7-2 shows the power supply cabling.
P3
P3
1 2 3 4
Power Supply
P1
Assembly
P1
(SP# 159447)
11 12 13 14 15 16 17 18 19 20
1 2 3 4 5 6 7 8 9 10
Conn. # Pin 1 Pin 2 Pin 3 Pin 4 P in 5 P in 6 P in 7 P in 8 P in 9 Pin 10
P1 +3.3 +3.3 RTN +5 RTN +5 RTN PwrGd +5 Aux +12
P1 [1] +3.3 -12 RTN PS On RTN RTN RTN FO +5 +5
P3 +12 GND GND +5
NOTES:
[1] This row represents pins 11-20 of connector P1.
All + and - values are VDC.
RTN = Return (signal ground)
GND = Power ground
PwrGd = Power Good
PS On = Power supply on
FO = Fan off
Figure 72. iPAQ 1.0/1.2 Power Cable Diagram
Compaq iPAQ Series of Desktop Personal Computers
7-4
Second Edition - February 2001
Technical Reference Guide
7.3.1.2 iPAQ 2.0 POWER DISTRIBUTION
The iPAQ 2.0 power supply assembly includes a multi-connector cable assembly that routes +3.3
VDC, +5 VDC, -5 VDC, +12 VC, and -12 VDC to the system board as well as to the individual
drive assemblies. Figure 7-3 shows the power supply cabling.
P3
P3
1 2 3 4
Power Supply
P1
Assembly
P1
(P/N 216922
or 218584) 8 9 10 11 12 13 14
1234567
Conn. # Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7
P1 +3.3 +5 RTN +5 RTN +5 RTN
P1 [1] +3.3 -12 FO PS On +5 Aux RTN +12
P3 +12 GND GND +5
NOTES:
[1] This row represents pins 8-14 of connector P1.
All + and - values are VDC.
RTN = Return (signal ground)
GND = Power ground
PS On = Power supply on
FO = Fan off
Figure 73. iPAQ 2.0 Power Cable Diagram
7-5
Compaq iPAQ Series of Desktop Personal Computers
Second Edition - February 2001
Chapter 7 Power and Signal Distribution
7.3.2 LOW VOLTAGE DISTRIBUTION
All iPAQ systems produce voltages less than 3.3 VDC (including processor core (VccP) voltage)
through regulator circuitry on the system board.
An on-board regulator produces the VccP (processor core) voltage according to the strapping of
signals VID3..0 by the processor. The possible voltages available are listed as follows:
VID 3..0 VccP VID 3..0 VccP
0000 2.05 VDC 1000 1.65 VDC
0001 2.00 VDC 1001 1.60 VDC
0010 1.95 VDC 1010 1.55 VDC
0011 1.90 VDC 1011 1.50 VDC
0100 1.85 VDC 1100 1.45 VDC
0101 1.80 VDC 1101 1.40 VDC
0110 1.75 VDC 1110 1.35 VDC
0111 1.70 VDC 1111 1.30 VDC
Compaq iPAQ Series of Desktop Personal Computers
7-6
Second Edition - February 2001
Technical Reference Guide
7 .4 SIGNAL DISTRIBUTION
Figures 7-4 and 7-5 show general signal distribution for an iPAQ 1.x and 2.0 system (respectively)
between the main subassemblies of the system unit in a standard configuration.
PW R Btn
Conn Power Button-
PW R LED
J8C1 LED Board
HD LED (PCA# 010647)
Mic Audio In
HP Audio Out
Conn
Audio-USB I/F
J2D1 Line Out Audio
Board
(PCA# 010650)
USB Tx/Rx 3
Conn
USB Tx/Rx 4
J7A1
+3.5, +/- 5,
+/- 12 VDC Power
Conn
Supply
System J8B1
Assembly
Board
(PCA # 161014 or
161015)
IDE I/F 5, 12 VDC
Pri. IDE
IDE
J7E1
Hard Drive
IDE I/F,
+5 VDC, Audio Daughter
Sec. IDE Multibay
Card
J8E1 Storage Device
(PCA #010644)
Mouse
Conn [1] Mouse
Kybd
Conn [1] Keyboard
Speaker Audio
Conn
NOTE:
[1] On legacy-light models, PS/2-type connector. On legacy-free models, USB connector.
Figure 74. iPAQ 1.0/1.2 Signal Distribution Diagram
7-7
Compaq iPAQ Series of Desktop Personal Computers
Second Edition - February 2001
Chapter 7 Power and Signal Distribution
Figure 7-5 shows signal distribution for an iPAQ 2.0 system in a standard configuration.
Graphics Data
Conn 4-MB
J113 Display Cache
(PCA# 011044)
+3.5, +/- 5,
+/- 12 VDC Power
Conn
Supply
P1
Assembly
IDE I/F 5, 12 VDC
Pri. IDE
IDE
P20
Hard Drive
System IDE I/F,
Board +5 VDC, Audio Multibay
Sec. IDE Multibay
(PCA # 011010) Board
P21 Storage Device
(PCA #011061)
Kybd Data
USB
Conn Mouse Data
J112 [1]
or
Kybd/Mouse Data PS/2
Legacy Mouse
Conn
Serial TX/RXData
Module
or
Conn. Legacy PS/2
Parallel Data
J90 Module Conn
Keyboard
Board
(PCA# 011013)
Conn. Audio
P6
NOTES:
Standard on legacy systems, optional on
legacy-free systems.
Standard on Pentium-based systems,
optional on Celeron-based systems.
[1] Suggested connection. May also use J110 or J112 .
Figure 75. iPAQ 2.0 Signal Distribution Diagram
Compaq iPAQ Series of Desktop Personal Computers
7-8
Second Edition - February 2001
Technical Reference Guide
Power Button/LED Header J8C1 Audio Header J2D1
(iPAQ 1.x) (iPAQ 1.x)
HD LED + 1 Mic Audio 1
2 Pwr LED + 2 Gnd
4 NC 4 NC
HD LED - 3 Mic Bias 3
Gnd 5
Gnd 5 6 Pwr Btn
Reset 7 HP Audio L 7
8 Gnd 8 Line Audio R
+5 Vcc 9 Line Audio L 9
10 ICH Service 10 HP Audio
NC 11 12 Gnd
Gnd 13
NC 15 16 NC
+5 Vcc
Not implemented
USB Header J7A2
(iPAQ 1.0/1.2)
Gnd 1 2 Gnd
4 Port 3 Data -
Port 3 Data + 3
+5 Vcc 5 6 +5 Vcc
Port 4 Data + 7 8 Port 4 Data -
Gnd 9
CD Audio Header P7
1 Ground
2 Audio (left channel)
3 Ground
4 Audio (right channel)
Serial Port A/COM1 Header J1G2
(Legacy-free iPAQ 1.x only)
Carrier Detect 6 Data Set Ready
RX Data 2 7 Request to Send
TX Data 3 8 Clear to Send
Data Terminal Ready 4 9 Ring Indicate
Ground 5
Figure 76. System Board Header Pinouts
7-9
Compaq iPAQ Series of Desktop Personal Computers
Second Edition - February 2001
Chapter 7 Power and Signal Distribution
This page is intentionally blank.
7-10 Compaq iPAQ Series of Desktop Personal Computers
Second Edition - February 2001
Technical Reference Guide
Chapter 8
BIOS ROM
8. Chapter 8 BIOS ROM
8 .1 INTRODUCTION
The Compaq iPAQ desktops use Compaq BIOS firmware loaded into the 82802 FWH component.
The BIOS ROM includes such functions as Power-On Self Test (POST), PCI device initialization,
Plug `n Play support, power management activities, and Setup. This chapter includes the following
topics:
iPAQ 2.0 features (8.2) page 8-2
Desktop management support (8.3) page 8-3
Memory detection and configuration (8.3) page 8-11
PnP support (8.5) page 8-12
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